Bob Stengel

A 100 MHz 2.5 GHz Direct Conversion CMOS Transceiver for SDR Applications

This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz - 2.5 GHz with channel bandwidths from 8 KHz to 20 MHz. At 1.8 GHz the receiver noise figure is 7 dB with IP3 of -6 dBm and voltage gain of 48 dB. The transmitter has better than 40 dB carrier suppression, 35 dB sideband suppression, and EVM of 1% at 800 MHz. The frequency synthesizer uses direct digital synthesis to achieve instantaneous frequency switching and phase noise of -123 dBc/Hz at 25 KHz offset.

A 6 watt LDMOS broadband high efficiency distributed power amplifier fabricated using LTCC technology

A novel new approach in designing high efficiency power distributed amplifiers for broadband wireless applications has been developed. This synthesis technique allows the designer to achieve power added efficiencies, during class B operation, greater than 50% while still preserving the low VSWR and broadband characteristics of distributed structures. The performance of these newly designed amplifiers can yield the same PAE and power output performance of narrow band, single-ended, reactively matched amplifiers, without the high sensitivity to manufacturing variations. This synthesis technique has been applied to develop LDMOS and PHEMT distributed power amplifiers for cellular base stations and portable communication applications.

Neutralized differential amplifiers using mixed-mode S-parameters

Distributed amplifiers offer very broadband operation, with the promise of a single all-band wireless solution. However, there are a number of distributed amplifier specific issues that have blocked practical implementation in a portable product. One of these is potential instability exacerbated by 20:1 antenna load impedance variation over a very broad frequency range of interest. This paper provides a neutralized differential amplifier implementation supported by mixed-mode S-parameters technology that offers a broadband stability solution for distributed amplifier application. Measurement results of a single section differential amplifier are included using Motorolas CDR1 BiCMOS technology.

A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter

A novel self-calibrating high-resolution digital-to-time converter (DTC) achieves 1024 individual phase states with a resolution of 0.5 ps. The phase interpolation is done in steps, by using a cascade of coarse active delay locked line and a passive programmable fine delay. The DTC is capable of self-calibration by using an integrated dual mixer time domain (DMTD) circuit to overcome device mismatch and process variations. The DTC is constructed using 90 nm standard digital CMOS technology at 1 GHz RF frequency. Future improvements are expected to increase the resolution to 0.1 ps and below.

Controlled dither in 90 nm digital to time conversion based direct digital synthesizer for spur mitigation

Dithering is used in many discrete to continuous value conversion functions to provide an effective fractional value. This paper reviews the application of dither to a digital-to-time converter (DTC) based digital synthesizer suitable for many common wireless communication systems. Measurements of a 90 nm CMOS implementation using a 5 bit DTC show extension to effective 8 bits.

Distributed Amplifier with Narrowband Amplifier Efficiency

A fully integrated tapered output line distributed cascode SiGe HBT amplifier is presented which presents an identical load to each transistor. A nodal analysis of currents in the output transmission line gives insight into the often assumed efficiency/bandwidth trade-off of a distributed amplifier. The four section one half watt amplifier with 50 Omega input and output exhibits a gain of 21 dB from 100 to 800 MHz with a saturated collector efficiency of 79% at 100 MHz.

RF power amplifiers for portable communication applications

We review the requirements of a power amplifier used in portable communication applications. The talk time or battery life of a portable unit is directly related to the transmitter RF conversion efficiency. The introduction of GaAs MESFETs, HFETs, and HBTs into portable communications equipment increased the performance level of RF power functions. The effect is a significant improvement in DC to RF conversion efficiency over the previous bipolar RF power amplifiers. Circuit applications and trade-off of MESFETs, HFETs and HBTs for portable communication system is also discussed.<<ETX>>

Distributed Power Amplifier with electronic harmonic filtering

Providing all band power amplification and harmonic rejection are objectives with orthogonal implementations. This paper is a review of a new Distributed Power Amplifier (DPA) architecture using programmable frequency dispersion. This frequency domain dispersion is designed to achieve electronic harmonic filtering within the intended frequency band. Tunable reactive components are not practical in a high power transmitter network. Instead vector signal combining is used to provide very narrow band destructive harmonic cancellation while the vector signal processing for the fundamental is constructive. This is a novel technology that enables an all band Software Defined Transmitter suitable for portable battery power communications equipment.

A low power 100 MHz – 2.5 GHz digital-to-time conversion based transmitter for constant-envelope direct digital modulation

This paper reports a flexible direct digital modulation based low power transmitter in 90 nm CMOS that supports constant-envelope modulation using phase or frequency modulation for carrier frequencies from 100 MHz to 2.5 GHz. For rectangular filtered 8-PSK modulation from 1 K symbol/s to 20 M symbol/s the RMS phase error is less than 4 deg. Frequency modulation is measured via filtered frequency shift keying (FSK) schemes used in two common standard protocols, GSM and APCO-25. GSM phase error at 800–900 MHz as well as 1900 MHz is less than 1 deg RMS. APCO-25 FSK error is less than 2% across bands from VHF (∼130 MHz) to UHF (∼400 MHz) to 800 MHz. Measured adjacent channel power ratio (ACPR) are within specification. The synthesizer power drain is 130 mW with an active area of 0.7 mm2.

A 90nm Quadrature Generator with Frequency Extension up to 4GHz

A 90nm CMOS design generates differential quadrature signals (I, In, Q, Qn) from 500MHz to 4GHz dissipating 26mW. A differential half wavelength DLL is used that reduces power dissipation, sideband noise and random unit delay error accumulation by a factor of 2 compared to full wavelength DLL designs. A custom combinatorial logic circuit extends the input frequency 500MHz to 1GHz up to 4GHz. Programmable charge pump current and series delay were added to compensate the differential quadrature duty cycle and quadrature accuracy at a transceiver measurement level.