Young-Su Kwon

Fast development of source-level debugging system using hardware emulation

We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

Communication-efficient hardware acceleration for fast functional simulation

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.

MetaCore: an application specific DSP development system

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.

MetaCore: an application-specific programmable DSP development system

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

Systematic functional coverage metric synthesis from hierarchical temporal event relation graph

Functional coverage is a technique for checking the completeness of test vectors in HDL simulation. Temporal events are used to monitor the sequence of events in the specification. In this paper, automatic generation of temporal events for functional coverage is proposed. The HiTER is the graph where nodes represent basic temporal properties or subgraph and edges represent time-shift value between two nodes. Hierarchical temporal events are generated by traversing HiTER such that invalid, or irrelevant properties are eliminated. Concurrent edge groups make it possible to generate more comprehensive temporal properties and hierarchical structure makes it easy to describe large design by combining multiple subgraphs. Automatically generated temporal events describe almost all the possible temporal properties of the design under verification.

A new single-clock flip-flop for half-swing clocking

We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of this logic cannot be ignored. In the proposed scheme, only NMOS devices are clocked with a half-swing clock in order to make it operate without the level converter or any other additional logics, and the random logic circuits except for the clock and flip-flops are supplied by V/sub cc/ while the clock network is supplied by V/sub cc//2. Compared to the conventional scheme, a great amount of power consumed in clocking which is responsible for a large portion of total chip power can be saved with the proposed new flip-flop configuration.

MDSP-II: a 16-bit DSP with mobile communication accelerator

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-/spl mu/m triple-layer metal CMOS process on a 9.7/spl times/9.8 mm/sup 2/ silicon area and was operated up to 50 MHz clock frequency.

Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus

Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms.

Pyramid texture compression and decompression using interpolative vector quantization

Texture mapping is a common technique used to increase the visual quality of 3D scenes. As texture mapping requires a large amount of memory to deal with large textures generally required in the current visual systems, we propose an algorithm for compressing a pyramid texture used for mipmapping. Vector quantization is used to compress all levels of the pyramid texture to one representative value databook, one residual codebook and one index map. The proposed compression scheme uses interpolative texel difference vector quantization that compresses the difference between the interpolated surfaces generated by the representative value and the correct uncompressed texels of the texture at each level. The compressed pyramid texture can be accessed randomly and decompressed without loss of visual quality. We also propose a hardware architecture that performs the trilinear filtering with the compressed pyramid texture.

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics

This paper presents a special hardware implementation developed for the computation of the specular term which is the most time consuming part in the Phongs illumination. In the Phong shading, the exponentiation operation of two floating-point numbers is necessary for each point inside a polygon. An approximation algorithm is developed to speed up the exponentiation operation, and it is supported by simple hardware that can be easily merged into a floating-point multiplier. The exponentiation operation takes just 4 cycles in the proposed hardware while it takes about 100-200 cycles in conventional floating-point units. Although an approximation algorithm is employed for the exponentiation operation, the amount of error is so minimal that the difference is virtually indistinguishable.