Boon-Khim Liew

Projecting interconnect electromigration lifetime for arbitrary current waveforms

A vacancy-relaxation model is proposed. It predicts the DC lifetime, pulse DC (arbitrary unidirectional waveform) lifetime, pure AC lifetime, and AC-plus-DC-bias lifetime for all waveforms and all frequencies above 1 kHz. The predictions are verified by experiments and significantly raise the projected lifetimes beyond the widely assumed A/sub dc/ T/J/sub rms//sup m/. The pure AC lifetimes of aluminum interconnect are experimentally found to be more than 10/sup 3/ times larger than DC lifetime for the same current density. In addition, AC stress lifetimes are observed to follow the same dependences on current magnitude and temperature, for T >

Electromigration interconnect lifetime under AC and pulse DC stress

A vacancy relaxation model which predicts the DC lifetime, pulse DC lifetime, and AC lifetime for all waveforms and all frequencies above 10 kHz is proposed. The AC lifetimes of aluminum interconnect are experimentally found to be more than 10/sup 3/ times larger than DC lifetime at the same current density. AC stress lifetimes have the same dependences on current magnitude and temperature, for T >

Modeling and optimization of substrate resistance for RF-CMOS

A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.

An analytical model of positive HBM ESD current distribution and the modified multi-finger protection structure

In order to study the ESD zapping current distribution variation with the well pick-up layout, a new transmission-line equivalent-circuit model is proposed which includes the effects of parasitic bipolar transistors and the horizontal and vertical P-well resistance. Based on this equivalent circuit and from real-time I-V characteristics during ESD zapping (Duvvury and Diaz, 1992), an analytical solution can be derived. For conventional multi-finger structures, it shows that the maximum current or power density of the device under the ESD zapping event is located at the region near the P-well pick-up. This model prediction is consistent with the devices damage sites after ESD zapping. Based on this model, a novel protection structure leading to uniform current distribution can be achieved by inserting P/sup +/ diffusion into each source region of NMOS devices. From the real-time I-V characteristics during ESD zapping, a new phenomenon termed the self-biasing effect is also observed. In order to sustain sufficient substrate potential to keep the bipolar turn-on, the devices snapback voltage should increase to generate more impact ionization current when the effective substrate resistance decreases. We observed the phenomenon that snapback voltage is varied with the device layout. As a result, higher snapback voltage may not lead to lower ESD threshold voltage.

Effects of self-heating on integrated circuit metallization lifetimes

The authors present simulation results, an experimental technique, and a model for estimating the temperature rise and time-to-failure (TTF) of interconnect. They introduce the concept of derating factor for electromigration TTF due to self-heating. The derating factor is the factor by which the lifetime is reduced by temperature rise in the interconnect. It is shown that in the limit of high frequencies, the temperature rise can be estimated in a straightforward manner using the root-mean-square current density after the thermal resistance of the structure has been determined from DC measurements. The implication of the temperature dependence on J/sub rms/ for the usually quoted J/sub ave/ design rule was examined. It was determined that self-heating is probably not significant for the usual design rule average current density of 1*10/sup 5/ A/cm/sup 2/ for operation at frequencies >10 MHz and duty factors >0.1%. However, if the design rule is increased to 1*10/sup 6/ A/cm/sup 2/, self-heating might become significant.<<ETX>>

Reliability simulator for interconnect and intermetallic contact electromigration

A previously developed model for predicting interconnect electromigration time-to-failure under arbitrary current waveforms is shown to be applicable to Al-W intermetallic contacts as well. This model is incorporated in a circuit electromigration reliability simulator which can (1) generate layout advisory for width and length of each interconnect, the safety factor of each contact and via in a circuit to meet user-specified reliability requirements and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure.<<ETX>>

Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices

Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFETs with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced, as compared to the one without TED. The reason is that the TED effect can yield a more graded n/sup -/ LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field and current flow distributions have been conducted. The phosphorus TED effects on transistor driving current and off-state leakage current are also investigated.

Circuit reliability of hot electron induced degradation in high speed CMOS SRAM

The access time degradation of a high-speed 256K CMOS SRAM (static random-access memory) is measured after high voltage stress. The circuit performance degradation due to hot electron effects is measured using BERT (Berkeley Reliability Tool), a circuit reliability simulator. Propagation delay between internal nodes is experimentally measured to verify the simulated result. No degradation is observed after a V/sub c//sub c/ = 6.5 V burn-in. This is in agreement with the simulated result. Simulation predicts that access time degradation in the 256 K SRAM (after 10 years product lifetime at V/sub c//sub c/ = 5.5 V) is 0.44 ns in the present 0.8 /spl mu/m technology. A similar analysis on the next 0.5 /spl mu/m generation of technology estimates an access time degradation of 1.45 ns.

Modeling electromigration lifetime under pulsed and AC current stress

Electromigration lifetime under DC current stress is now routinely measured to support new metallization process development as well as to monitor the control of an existing process. The measured DC lifetime value, or design rule, is the only link between process technology and circuit design for metal reliability. This paper reviews a defect relaxation model for pulsed DC (non-alternating) current stress lifetime and a damage-healing model for AC (bidirectional) current stress lifetime. The purpose is to model the metal reliability of ICs. Both models significantly raise the predicted lifetime beyond the predictions of some previous models.

The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability

The electrostatic discharge (ESD) failure threshold of an output buffer is observed to be sensitive to the used-gate finger number. It is found that the lower the current drive capability, the lower the ESD failure threshold, and the damage sites of the output buffer are always located at the used gate n-channel metal-oxide semiconductor (NMOS) transistors. This observation can only be explained on the basis of the energy dissipation (E=VSP×ID×time) in each finger, where ID is composed of channel current and bipolar current. From the real-time current-voltage measurement during ESD zapping, three phenomena are observed. The first is that a transistor with a floating gate (used-gate fingers) has a larger snapback voltage (VSP) than that with a grounded gate transistor. The second is that due to the accumulation of hot holes in the floating gate, a constant gate voltage can be induced during the ESD zapping. The last is that this induced-gate-voltage can assist the switching on of the NMOS transistors and reduction of the ESD duration. Therefore, the ESD duration of a transistor with high current drive capability will be much shorter than that of low current drive capability. As a result, high current drive capability leads to a high ESD failure threshold.