Jiaw-Ren Shih

An analytical model of positive HBM ESD current distribution and the modified multi-finger protection structure

In order to study the ESD zapping current distribution variation with the well pick-up layout, a new transmission-line equivalent-circuit model is proposed which includes the effects of parasitic bipolar transistors and the horizontal and vertical P-well resistance. Based on this equivalent circuit and from real-time I-V characteristics during ESD zapping (Duvvury and Diaz, 1992), an analytical solution can be derived. For conventional multi-finger structures, it shows that the maximum current or power density of the device under the ESD zapping event is located at the region near the P-well pick-up. This model prediction is consistent with the devices damage sites after ESD zapping. Based on this model, a novel protection structure leading to uniform current distribution can be achieved by inserting P/sup +/ diffusion into each source region of NMOS devices. From the real-time I-V characteristics during ESD zapping, a new phenomenon termed the self-biasing effect is also observed. In order to sustain sufficient substrate potential to keep the bipolar turn-on, the devices snapback voltage should increase to generate more impact ionization current when the effective substrate resistance decreases. We observed the phenomenon that snapback voltage is varied with the device layout. As a result, higher snapback voltage may not lead to lower ESD threshold voltage.

The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability

The electrostatic discharge (ESD) failure threshold of an output buffer is observed to be sensitive to the used-gate finger number. It is found that the lower the current drive capability, the lower the ESD failure threshold, and the damage sites of the output buffer are always located at the used gate n-channel metal-oxide semiconductor (NMOS) transistors. This observation can only be explained on the basis of the energy dissipation (E=VSP×ID×time) in each finger, where ID is composed of channel current and bipolar current. From the real-time current-voltage measurement during ESD zapping, three phenomena are observed. The first is that a transistor with a floating gate (used-gate fingers) has a larger snapback voltage (VSP) than that with a grounded gate transistor. The second is that due to the accumulation of hot holes in the floating gate, a constant gate voltage can be induced during the ESD zapping. The last is that this induced-gate-voltage can assist the switching on of the NMOS transistors and reduction of the ESD duration. Therefore, the ESD duration of a transistor with high current drive capability will be much shorter than that of low current drive capability. As a result, high current drive capability leads to a high ESD failure threshold.

Mechanism of instability on device's characteristics due to intermetal dielectrics with low-k material and the modified process

In this paper, the effects of back-end process on device characteristic shift are explored. It had been found that the transistors with different inter-metal-dielectric (IMD) films have different performance. Moreover, more of the IMD layers will result in more of the electrical characteristic shifts. The shift is dominated by the interface state reduction. The mode of plasma-enhanced hydrogen out- diffusion during IMD film deposition is proposed to explain the BEOL-relate device shift. In order to relive this effect of electrical characteristic shift, another alloy step by pure hydrogen anneal is implemented after metal-1 etch and before the Via-1 deposition. It is found the electrical characteristics taken at metal-1 stage are very close to those taken at melal-6 with passivation step. In addition, there is no apparent hot carrier lifetime degradation with or without the pure hydrogen treatment.

A novel thin gate-oxide-thickness measurement method by LDD (lightly-doped-drain) NMOS (N-channel metal-oxide-semiconductor) transistors

In this paper, we propose a novel thin gate-oxide-thickness measurement method by using Lightly-Doped-Drain (LDD) N-Channel Metal-Oxide-Semiconductor (NMOS) snapback characteristics. For device with thin oxide 150 A~60 A and optimized LDD doping profile, the drain breakdown voltage will be oxide-thickness limited, and therefore the oxide breakdowns critical-field is about 10 MV/cm. By this characteristic, as high-voltage sine-waveform generator provides the necessary voltage to lead to the grounded-gate LDD-NMOS happening gate-assisted drain breakdown and drives its parasitic n-p-n bipolar turn-on. The voltage-waveform collapses immediately as the applied-voltage exceeds the critical oxide-field 10 MV/cm. Therefore, the oxide thickness can be determined.