Kit Man Cham

Self-Limiting Behavior of Hot Carrier Degradation and Its Implication on the Validity of Lifetime Extraction by Accelerated Stress

The time dependence of hot carrier degradation of n-channel MOSFETs and the methodology of accelerated stress have been investigated in detail. The time (T) dependence is found to be inconsistent with the simple expression of TN (N-0.25), but rather show a slow-down of the degradation rate. The slope of the degradation curve is also found to be dependent on the stress bias voltage. The projection of device lifetime by accelerated stress based on the TN law and the assumption of constant slope independent of stress bias is unreliable.

Test structures for characterization and comparative analysis of CMOS image sensors

A set of test structures designed to characterize and compare the performance of CMOS passive and active pixel image sensors is presented. The test structures are deigned so that they can be rapidly ported from one process to another. They are also designed so that individual photodetectors and pixel circuits as well as entire image sensor arrays can be characterized and compared based on: quantum efficiency, spectral response, fixed pattern noise, sensitivity, blooming, input referred read noise, reduction of quantum efficiency caused by silicide/salicide, lag, digital switching noise sensitivity, impact ionization noise sensitivity, dynamic range, and temperature dependency of all measured parameters. Four test chips that include a variety of these structures have been built in two different 0.35 micrometer CMOS processes. The test chips include nineteen types of individual photodetectors and thirty eight types of 64 by 64 pixel arrays. The test methodology and preliminary test results from these chips are presented.

Characterization and modeling of the trench surface inversion problem for the trench isolated CMOS technology

The trench surface inversion problem for the trench isolated CMOS technology was studied with special emphasis on the N-well CMOS technology where the problem is most severe. Using special trench surface inversion test structures, the charge density (Qss) at the trench surface has been determined to be about 2E11 cm-2. Latch-up characteristics of trench isolated structures are also characterized. Two dimensional simulations of the trench isolation structure show that Qssalong the trench surface has to be maintained at 5E10 cm-2if the substrate doping concentration remains at 6E14cm-3. To prevent trench surface inversion, higher substrate doping, lower N-well bias and more negative substrate bias are recommended. Trench isolation is more suitable for P-well or N-well with p/p+ epi technologies.

The dependence of hot carrier degradation on AC stress waveforms

The hot carrier degradation of submicron n-channel FETs is characterized for various gate and drain pulse waveforms. The results are consistent with interface electron traps generated by hot holes. The results showed that inverters with small loads can degrade faster than inverters with large loads, due to AC degradation effects. Device lifetime in circuits cannot in general be projected by DC data. The AC effect was also found to be dependent on device structure. >

Fabrication and characterization of sub-micron thin gate oxide p-channel transistors with p+ polysilicon gates

Submicron p-channel transistors have been fabricated using thin (150 A) gate oxide and p+polysilicon gates. Quite favorable device characteristics have been achieved for L(eff) as low as 0.4 microns. GEMINI simulations have been performed which demonstrate the advantages of p+poly in reducing short channel effects and punchthrough problems. Experimental results from three separate device lots show good subthreshold slope and low leakage current, even for low threshold voltages. Vt vs. L(eff) shows much less threshold drop than is seen using n+ poly. Device characteristics are robust with respect to processing variations. CV data shows little if any boron penetration through the 150 A gate oxide.

An Automated Test System for MNOS Transistor Characterization

An automated and thorough characterization of MNOS transistors has been made possible by using a calculator-based instrumentation system. Fast pulse techniques are used to obtain maximum information and minimize reading disturbance during measurements. Device characteristics such as retention, endurance, and mobility can be obtained with minimal manual interaction.

An improved automatic test system for VLSI parametric testing

Automated and thorough characterization of MOS transistors has been made possible by using a minicomputer-based instrumentation system. A low-current circuit capable of forcing current levels down to the range of 10 pA has been designed on the personality board, allowing fast measurements of subthreshold characteristics. A comprehensive test program has been developed to extract device parameters, such as threshold voltage, subthreshold slope, intrinsic mobility, mobility degradation, effective-channel doping, body effect, ΔL, ΔW, series resistance, and carrier-saturation velocity. Data management software also provides detailed statistical analysis. The technique is found to be a powerful and essential tool for VLSI process development.

Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture

CMOS image sensors are very suitable for battery-operated camera systems due to their low power nature. In this research work, a salient integration mode CMOS image sensor pixel design which requires only 1 or 2 transistors per pixel and a low power readout architecture was developed in a 0.35 /spl mu/m CMOS technology. High fill factor and small pixel size are achieved at the same time for the 2T pixel design. The readout architecture includes a low voltage low power multi-stage analog data buffer which works as a differential to single-ended conversion mechanism for a new correlated double sampling method. Total data bandwidth and switching power are also greatly reduced. The architecture was developed to be scalable to 0.18 /spl mu/m technology with 1.2 V supply voltage, and lower. An experimental chip in an array size of 256/spl times/256 with a pixel size of 63 /spl mu/m/spl times/6.3 /spl mu/m was fabricated in HPs 0.35 /spl mu/m CMOS technology. Promising experimental results strongly indicate that the new pixel design and readout architecture are suitable for low voltage CMOS camera chips in future generations of CMOS technology.

Optimization of sub-micron p-channel FET structure

The effect of the counter-doping channel implant junction depth (Yj) and the source/drain junction depth (Xj) on the subthreshold characteristics of submicron p-channel transistors are analyzed using simulation methods. Results indicate that submicron p-channel transistors must have shallow junctions, 0.1 to 0.15um for both Xj and Yj, in order to achieve good subthreshold characteristics. Based on these results, a process was designed. Arsenic channel implant was used for controlling Yj to within 0.1um deep. Shallow p+source/drain junctions (0.1um) were formed with boron implant and low temperature annealing. Good subthreshold slope (80-90mV/ decade) and large punch-through voltage (5V) were measured from devices having an effective channel length (Leff) of 0.4um and a threshold voltage (Vt) of -0.6V.

Methodology in Computer-Aided Design for Process and Device Development

The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.