Brecht François

Highly Linear Fully Integrated Wideband RF PA for LTE-Advanced in 180-nm SOI

A highly linear fully integrated RF power amplifier (PA) for advanced long-term evolution (LTE-advanced) is fabricated in a 180-nm standard silicon-on-insulator process. To improve the linearity, several harmonic traps are introduced to minimize the second- and third-order harmonics, and hence, the third-order intermodulation distortion (IMD3). The impact on the linearity of the RF PA of each of the harmonic controls is studied and simulated. Finally, both the linearity of a standalone RF PA and an RF PA with proposed linearity enhancement circuitry is investigated by comparing their measured IMD3. For an LTE uplink signal with 20-MHz signal bandwidth and a 64-QAM 8.7-dB peak-to-average power ratio, the RF PA achieves 21.7% power-added efficiency (PAE) with 11-dB gain while delivering an average output power of 22.4 dBm in LTE-band VII. Simultaneously, the RF PA obeys the stringent spectral mask and the -30-dBc adjacent channel leakage ratio linearity requirement and achieves an error vector magnitude of only 4.05%. The linearized wideband RF PA is also verified for LTE-band I and achieves similar performance from 1.9 to 2.8 GHz. Thanks to the applied linearization technique, the proposed RF PA is able to transmit an LTE-advanced (release 12) signal with a carrier-aggregated bandwidth up to 60 MHz while satisfying the linearity requirements. For a 40-MHz (2 × 20 MHz) and 60-MHz (3 × 20 MHz) LTE-advanced signal at band VII, the RF PA produces an average output power of 19.2 and 17.6 dBm while achieving a PAE of 17.2% and 13.7%, respectively.

A CMOS Burst-Mode Transmitter With Watt-Level RF PA and Flexible Fully Digital Front-End

A fully digital burst-mode handheld transmitter with power amplifier for the 900-MHz band is presented. The transmitter front-end consists of a digital polar modulator which uses pulse width modulation (PWM) for the amplitude modulator. Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequency clock signals. The modulated signal is amplified by a Class B amplifier which uses power combining to reach watt-level output power. The transmitter is implemented in standard CMOS technology. When transmitting a modulated signal with a peak-to-average power ratio (PAPR) of 10.3 dB and 5-MHz bandwidth, the burst-mode transmitter meets the stringent error-vector-magnitude (EVM) specifications of 5.6% at 23.1-dBm average output power with 11.7% power added efficiency (PAE).

Analysis and Optimization of Transformer-Based Power Combining for Back-Off Efficiency Enhancement

This paper analyzes the back-off efficiency enhancement characteristics of transformer combined power amplifiers taking into account the amplifier and transformer parasitics. The dynamic power combining properties of different transformer architectures are investigated. The co-optimization of the transformer and the amplifiers is presented for the transformer-based Doherty power amplifier which is a linear class of operation with back-off efficiency enhancement. Then this analysis is extended for the uneven Doherty power amplifier which employs asymmetrical transformers. The proposed design methodology is used to design a 2.4 GHz uneven Doherty power amplifier in standard 90 nm CMOS technology. The fabricated two stage Doherty amplifier achieves 26.2 dBm peak output power at 2 V supply. The measured peak drain efficiency of the PA is 37% while the efficiency at 6 dB back-off is still as high as 30.1%.

CMOS RF PA design: Using complexity to solve the linearity and efficiency trade-off

Some important aspects of CMOS RF PA design are discussed. Improving efficiency at circuit level is discussed first, as well as the challenge to achieve high output power in low-voltage CMOS. Next, some PA architectures are reviewed. It will be shown how signal processing can be used to improve the efficiency of a CMOS PA.

A fully integrated CMOS power amplifier for LTE-applications using clover shaped DAT

In this paper, a Distributed Active Transformer (DAT) is used to implement a fully-integrated RF power amplifier (PA) for the extended GSM-band and LTE band VIII in a standard 90 nm CMOS process. The DAT allows the designer to integrate both the input and output matching networks as the power combining itself on the same silicon die. The PA delivers up to 29.4 dBm of RF power with 28.4% drain efficiency and a power added efficiency (PAE) of 25.8% by using a 2 V supply voltage. The PA is measured for both GSM-signals and LTE-signals. For GSM, the maximum output power is 29.1 dBm. The corresponding output spectrum at 400 kHz and 600 kHz frequency offset is −68 dBc and −70 dBc and meets the spectral mask requirements. The Power versus Time (PvT) measurement shows that the time domain constraints are met. When applying a LTE-signal with 10 MHz bandwidth and a PAPR of 6.92 dB to the RF PA, the designed PA meets the EVM specification at 25 dBm average output power with 15% PAE.

A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS

This paper introduces a fully integrated direct power detector that monitors both RF current and RF voltage to detect the RF output power of the on-chip RF PA realized in a standard 40 nm CMOS process. The RF current measurement is realized by a sense winding in the output transformer, while the RF voltage waveform measurement is performed by capacitive division of the RF output voltage. Since the RF current and the RF voltage are both acquired, this power detector accurately and continuously determines the real output power of the RF PA with a maximum inaccuracy of ±0.5 dB over a wide 32.5 dB dynamic range. This power detector was integrated together with a 5 GHz RF PA designed for the WLAN IEEE 802.11ac communication standard. The power detector is capable of performing a RF output power measurement even for an antenna impedance mismatch up to voltage standing wave ratio (VSWR) 2.8:1 with an accuracy of ±1 dB, which allows the power detector to be used in an automatic antenna-mismatch correction system to prevent performance degradation in the RF PA. Finally, since the proposed power detector can be completely incorporated inside the RF PA output transformer. It results in zero area overhead, proving a very cost effective design.

3.3 A transformer-coupled true-RMS power detector in 40nm CMOS

To optimize the power consumption and system performance of battery-supplied devices, it is required to monitor and adjust the transmitted RF power accurately and continuously. This is typically done by an external power detector (PD), which increases area and cost. On the other hand, fully integrated power detectors are typically voltage-based [1-5] and only give the correct RF output power for a fixed load impedance. But in practice, antenna impedance variations will occur, causing VSWR mismatches that introduce an error in these voltage-based RF output power measurements. This paper presents a 5GHz WLAN PA with an on-chip true-RMS Power Detector, without any additional power loss or area overhead. The power detector is based on a magnetically coupled sense winding and takes advantage of transformer-based power combining and impedance transformation that has become common practice in nanometer CMOS RF PAs. The proposed power detector performs both an RF voltage and RF current measurement at the PA output and is therefore capable of performing a True power measurement, even under VSWR mismatches or load variations. This proposed power detector is implemented in 40nm standard CMOS and unlike earlier reported power detectors [1-4], it is integrated together with a 5GHz RF PA targeting the WLAN (IEEE 802.11a) communication standard.

Efficiency Enhancement Techniques for RF and MM-Wave Power Amplifiers

Some important aspects of CMOS RF PA design are discussed. First the reader is confronted with the ever prominent efficiency-linearity trade-off in the design of conventional amplifier classes, such as A and B, as well as the challenge to achieve high output power in low-voltage CMOS. To cope with this challenge, several power combining structures are introduced. Next, some RF PA architectures are presented to improve the efficiency at power back-off. Finally, some recently introduced architectures are discussed that use the advanced signal processing capabilities of CMOS to deal with this efficiency-linearity trade-off in RF PA design.