Pieter A. J. Nuyts

A CMOS Burst-Mode Transmitter With Watt-Level RF PA and Flexible Fully Digital Front-End

A fully digital burst-mode handheld transmitter with power amplifier for the 900-MHz band is presented. The transmitter front-end consists of a digital polar modulator which uses pulse width modulation (PWM) for the amplitude modulator. Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequency clock signals. The modulated signal is amplified by a Class B amplifier which uses power combining to reach watt-level output power. The transmitter is implemented in standard CMOS technology. When transmitting a modulated signal with a peak-to-average power ratio (PAPR) of 10.3 dB and 5-MHz bandwidth, the burst-mode transmitter meets the stringent error-vector-magnitude (EVM) specifications of 5.6% at 23.1-dBm average output power with 11.7% power added efficiency (PAE).

A fully digital PWM-based 1 to 3 GHz multistandard transmitter in 40-nm CMOS

A fully digital 1 to 3 GHz multimode transmitter is presented which contains two RF modulators: One uses baseband (BB) PWM, while the other uses RF PWM. RF PWM produces less harmonics, while BB PWM has a higher dynamic range (DR) and consumes less power. The BB PWM system satisfies the WLAN EVM limit over the whole frequency range. The RF PWM system achieves sufficient EVM for standards such as EDGE and WCDMA. Both systems support the use of multiple PAs to extend the DR using multilevel PWM.

A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS

A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.

Frequency-Domain Analysis of Digital PWM-Based RF Modulators for Flexible Wireless Transmitters

This paper presents a frequency-domain analysis of the noise and distortion terms produced by a digital RF modulator that uses pulse width modulation (PWM) for the amplitude modulation and a square wave as RF carrier. Insight in these terms is important as they limit the error vector magnitude (EVM) the modulator can achieve. For each of the terms, frequency-domain expressions are derived which are valid as long as the quantization noise is small and the digital PWM is sufficiently close to natural-sampling PWM. The dependency of the terms on the different system parameters is estimated, and the calculations are supported and complemented with simulation results. The presented analysis improves the understanding of the dominant noise and distortion sources, which can significantly speed up the design of PWM-based transmitters.

Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission

Introduction.- Digital Transmitter Architectures: Overview.- High-Level Analysis of Fully Digital PWM Transmitters.- Continuous-time Digital Design Techniques.- A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA based on Baseband PWM.- A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D Pas using Baseband and RF PWM.- Conclusions and Future Work.

Continuous-Time Digital Design Techniques

Designing continuous-time digital circuits requires a design flow that is radically different from traditional, discrete-time digital design, which is usually based on hardware description languages (HDLs) and standard cells. In some aspects, continuous-time digital design is closer to analog design than to digital. However, since two-level signals are mostly used, most building blocks are digital gates, so that many digital design aspects are important as well. This chapter discusses the fundamentals of continuous-time digital design. It starts by motivating the use of continuoustime circuits in this work and discussing their advantages and disadvantages. Next, the basic concepts in continuoustime digital design are introduced using the most basic continuoustime circuit, the delay line. After treating delay lines, some other important lowlevel building blocks for continuoustime digital systems are presented, and finally a design flow for this type of systems is proposed

Digital Transmitter Architectures: Overview

This chapter gives an overview of different fully or partially digital transmitter architectures that have been presented in literature. These are classified according to different properties, and the main advantages and disadvantages for each type are investigated. This will motivate the use of continuous-time PWM-based polar transmitter architectures, which are the subject of the remainder of this work.

A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA Based on Baseband PWM

This chapter discusses a transmitter test chip that was produced in a 65-nm low-power CMOS technology. The chip contains a polar transmitter using baseband pulse width modulation (PWM) on the amplitude path. Phase modulation (PM) is implemented by applying a variable time shift to an externally applied square wave carrier. Both PM and PWM are based on unclocked digital delay lines. The chip targets carrier frequencies from 946 MHz to 2.4 GHz with signal bandwidths up to 20 MHz, and is designed to drive two differential class-E PAs, which both consist of two single-ended PAs in push–pull configuration.

A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D PAs Using Baseband and RF PWM

This chapter discusses a second test chip that was created in a 40-nm general purpose standard CMOS technology. The chip includes two different transmitter front-ends which share some building blocks: a baseband PWM and an RF PWM modulator. Putting both designs on a single chip allows a good comparison of their performance. In addition, producing a second baseband PWM modulator in a smaller CMOS technology than in Chap. 5 allows investigating the effects of technology scaling.

High-Level Analysis of Fully Digital PWM Transmitters

Digital transmitters approximate the ideal analog signals by digital signals, which introduces many nonidealities. On one hand, this results in noise and distortion in the signal band, which deteriorates the signal quality. On the other hand, it results in distortion peaks outside the signal band, which may interfere with signals in different communication bands. Both in-band and out-of-band nonidealities are governed by fairly complex effects that depend on a number of parameters. Understanding these effects is crucial in order to efficiently explore the design space and implement performant transmitter architectures. In order to speed up the design process, it would be practical if these nonidealities can not only be understood but also predicted. For certain effects, this can be done using analytical approximations. For other, more complex effects, simulations are still needed. This chapter gives a theoretical high-level analysis of the nonidealities that occur in different types of digital PWM-based transmitters and their effects on the output spectrum.