Brian Curran

High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes

Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 GHz, considering the slow-wave, dielectric quasi-TEM and skin-effect modes. The frequency ranges of these modes and their transitions are predicted using resistivity-frequency domain charts. The impact of the modes on signal integrity is quantified, and three coaxial TSV configurations are proposed to minimize this impact. Finally, conventional expressions for calculating the per-unit-length circuit parameters of transmission lines are extended and used to analytically capture the frequency dependent behavior of TSVs, considering the impact of the mixed dielectric (silicon dioxide-silicon-silicon dioxide) around the TSVs. Excellent correlation is obtained between the analytical calculations using the extended expressions and electromagnetic field simulations up to 130 GHz. These extended expressions can be implemented directly in electronic design automation tools to facilitate performance evaluation of TSVs, prior to system design.

A Methodology for Combined Modeling of Skin, Proximity, Edge, and Surface Roughness Effects

A methodology is introduced for modeling resistive losses in planar transmission lines that support the transverse electromagnetic mode. The methodology aims to accurately and systematically account for these losses by modeling the skin, proximity, edge, and surface roughness effects in a combined way. The results show a correlation with three measurements within 5%, and offer insight into the different sources of resistive losses at high frequencies. Considering a printed coplanar line as an example, approximately 8% of the resistive loss come from surface roughness, and 30% from the edge effects at 60 GHz. However, for a line with a higher conductivity metallization, this increases to 38% and 30%, respectively, from surface roughness and edge effects at only 20 GHz.

The impacts of dimensions and return current path geometry on coupling in single ended Through Silicon Vias

Through Silicon Vias (TSVs) are expected to play an increasingly important role in next-generation microelectronics packaging. Even when the challenge of attenuation is overcome, crosstalk remains a major concern in TSV design. In this paper, it is shown that, at frequencies above 20 GHz, near-end crosstalk can easily exceed −20 dB. Traditional analytical models for crosstalk are compared to full-wave simulations to determine their limitations and a lumped element equivalent circuit model is presented. An examination of the impact of TSV dimensions is presented. Then, three TSV structures are compared and the impact of their dimensions on crosstalk is investigated.

Managing Losses in Through Silicon Vias with Different Return Current Path Configurations

The high bulk conductivity of silicon, leading to high attenuation, will become a significant challenge for designers of silicon-based system-in-package modules. In this paper, losses in TSV interconnect schemes are quantified with full-wave simulations. Several techniques for optimizing transmission using different return current paths are investigated, including ground shielding vias and two coaxial via structures. Then, a comparison of the losses in structures with different return current paths is made.

On the quantification and improvement of the models for surface roughness

Predictability of transmission line parameters is very important for microelectronics packaging. Surface roughness can cause a drastic deviation in transmission line parameters from the ideal theoretically calculated values. State-of-the-art analytical and full-wave surface roughness models have been helpful in closing this gap but they have considerable limitations, especially when applied to certain types of thin-film structures. This work analyzes some state-of-the-art surface roughness models and quantifies their limitations. A new approach to surface roughness characterization is then presented.

On the quantification of the state-of-the-art models for skin-effect in conductors, including those with non-rectangular cross-sections

Predictability of transmission line parameters in both the frequency and time-domains is very important for microelectronics packaging. Proximity effects and non-rectangular cross-sections can cause a drastic deviation in transmission line parameters from the theoretically calculated values. Filament models and full-wave techniques have offered improvements over analytical models for computing the parameters of transmission lines with arbitrary cross-sections including proximity effects. This work is an analysis of some state-of-the-art skin-effect models and a quantification of their limitations.

Novel multimodal high-speed structures using substrate integrated waveguides with shielding walls in thin film technology

The viability of multimode high-speed transmission structures in 3D silicon system-in-package modules is examined with full-wave simulations. Multimode transmission is achieved by integrating a stripline into a dielectric filled waveguide built over a silicon substrate shielded with walls instead of the via fence used in the traditional substrate integrated waveguide (SIW) structure. Isolation and transmission properties are evaluated using the full-wave solver Ansoft HFSS. The improvement of shielding walls eliminates potential bandgaps, offers a more predictable response, and reduces attenuation at high frequencies by 10% on the TEM mode.

The impact of moisture absorption on the electrical characteristics of organic dielectric materials

Organic dielectric materials will absorb moisture when in direct contact with a liquid or a humid environment. The dielectric then becomes a two-phase dielectric composite with new dielectric characteristics. Using the Lichtenecker Equation, the composite dielectric permittivity and loss characteristics are modeled. The loss modeling includes the polymer dielectric loss characteristics, as well as the conductive loss of the moisture. The model is also used to predict the frequency dispersion of the relative permittivity at lower frequencies caused by the conductivity of the moisture. The modeling is validated using high frequency measurements of interdigital capacitors, which correspond to the modeling within 5% across the entire examined frequency range.

Design and Comparison of 24 GHz Patch Antennas on Glass Substrates for Compact Wireless Sensor Nodes

Three patch antennas suitable for integration and operation in a compact 24 GHz wireless sensor node with radar and communication functions are designed, characterized, and compared. The antennas are manufactured on a low loss glass wafer using thin film (BCB/Cu) wafer level processing (WLP) technologies. This process is well suited for 3D stacking. The antennas are fed through a microstrip line underneath a ground plane coupling into the patch resonator through a slot aperture. Linear polarization (LP), dual mode (DM) operation, and circular polarization (CP) are achieved through the layout of the slot aperture and rectangular patch dimensions. Antenna gain values of ∼5.5 dBi are obtained in addition to the 10 dB impedance bandwidths of 900 MHz and 1.3 GHz as well as 500 MHz CP bandwidth with a 3 dB axial ratio for the LP, DM, and CP patch antennas, respectively.

Electrical modeling of the power delivery to an LED array packaged in a textile

Recent technologies enable large arrays of LEDs to be integrated into textiles, which has applications in the lighting industry. Two analytical modeling techniques are proposed that calculate the supply power at a source necessary to provide the LED drivers with a minimum voltage. The modeling techniques show a correlation with numerical simulations to within 10% but can be implemented for very large LED arrays where, for time constraints, numerical simulations become impractical. The modeling allows a designer to optimize the location of the supply voltage, which can reduce the increase in voltage over the ideal voltage by 40%.