Richard B. Wunderlich

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena

We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor channel models. We use Address-Event Representation (AER) spike communication for inputs and outputs to this IC. We present the IC architecture and infrastructure, including IC chip, configuration tools, and testing platform. We present measurement of small network of neurons, measurement of STDP neuron dynamics, and measurement from a compiled spiking neuron WTA topology, all compiled into this IC.

A Programmable and Configurable Mixed-Mode FPAA SoC

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000 × higher density than other non-FG approaches.

Floating Gate-Based Field Programmable Mixed-Signal Array

We present the field programmable array of analog and digital devices (FPAADD) as a novel implementation of a field programmable mixed-signal array (FPMA). The FPAADD is a hybrid combination of a field programmable analog array (FPAA) and a field programmable gate array (FPGA). Unlike other FPMAs where the FPGA and FPAA portions are kept separate, this architecture closely integrates the two in a fine-grained interleaved array. Instead of using hard-coded data converters, the FPAADD synthesizes data converters out of its reconfigurable fabric. The analog and digital portions share a common global interconnect. Floating gate (FG) transistors are used as the switch and memory elements of the chip, providing better switch performance and power over traditional static random-access memory-based approaches. The precise programmability of the FG switches also allows for computation to take place in the interconnect. These key differences make the FPAADD much more general purpose than previous FPMA architectures. The FPAADD consists of 27 × 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 × 5 mm2 die fabricated in a 0.35- μm CMOS process, and contains more than 130 000 FG transistors.

Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA

We present a large-scale field programmable analog array that enables floating-gate (FG) adaptive circuits using FG-based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the signals. We present the experimental data (350-nm commercial CMOS process) for a single-transistor adaptive structure, for a compiled autozeroing amplifier, and for multiple adaptive FG circuits.

Neuron Array With Plastic Synapses and Programmable Dendrites

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Programmable floating-gate techniques for CMOS inverters

The use of analog floating-gate elements in analog circuit research has steadily increased. These elements have great potential because they can be fabricated on a standard process and are low-power. An interesting application for these circuits is in the tuning of digital circuits for threshold and power consumption, which has been traditionally done by design. We explore the use of analog floating gates for threshold adjustments in a digital inverter.

Passgate resistance estimation based on the compact EKV model and effective mobility

A method to approximate nFET passgate resistance using the compact EKV model is presented. The model picks a mobility that has a greater effect on channel current than higher-order MOS effects in order to approximate the worst-case current over a drain-source voltage range. The model is compared to data taken from an IC that was fabricated in a 0.5µm, scalable CMOS process available through MOSIS.

Capacitively-Biased Floating-Gate CMOS: a New Logic Family

Given a particular digital logic path and a desired operating frequency there exists an optimal trade off of dynamic, static, and short-circuit power dissipation. Techniques like DVS and variable thresholds exist to bring paths closer to this optimum, but intrinsic complications limit how close they can get. We present capacitively-biased, floating-gate CMOS (FG-CMOS) as a new, and intrinsically more efficient, logic family that removes many of these complications as well as giving rise to new dimensions of design and run time optimizations previously unattainable. Simulations are performed to explore the energy per cycle versus cycle time of arbitrary digital logic paths, and show FG-CMOS capable of running atleast 12% faster at the same power, or at 36% less power at the same speed, or when 20% slack is introduced 65% less power than regular CMOS or 37% less power than DVS CMOS. Devices were fabricated to show functionality, explore area ramifications, and to validate simulation.

A large-scale FPAA enabling adaptive floating-gate circuits

We present a large-scale Field Programmable Analog Array (FPAA) that enables floating-gate adaptive circuits using Floating-Gate(FG) based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the resulting signals. We present experimental data for the basic adaptive structure and for a compiled AFGA.