Brian VanVoorst

Gigabit switch using free-space and parallel optical data links for a PCI-based workstation cluster

Communication requirements in high-performance, parallel computing systems continue to increase as the processing nodes within these systems gain processing capability. To support these growing communication requirements, system architecture changes are needed. The use of switched networks rather than bus-based systems and the incorporation of optical interconnects are among proposed solutions to increase overall system performance. Under the VIVACE program, we combine both of these approaches to demonstrate a switched network of 12-Gb/s raw data bandwidth using a 4 Tbit/s bisection bandwidth free-space optically interconnected (FSOI) switch. The optical-interconnect based VIVACE network is accessed by compute nodes through the use of an electrical network interface card (NIC) which provides custom VIVACE protocol conversion in addition to the necessary electrical and optical conversions.

High-speed free-space scalable switching network for parallel computing

The system architecture and the first prototype demonstrator system for the VCSEL-based Interconnects in VLSI Architectures for Computational Enhancement (VIVACE) program is described. The main goal of the VIVACE program is to build a high bi-section bandwidth free-space optically interconnected switch and to demonstrate it in a system of multiple compute nodes running a distributed algorithm. The prototype demonstrator system developed is a stand alone first-generation VIVACE Optical Network Interface Card (VONIC) communicating to another VONIC through a parallel- data fiber link. This system was developed to test the signal integrity and Bit Error Rate between two VONICs.

ARM: Anticipated route maintenance scheme in location-aided mobile ad hoc networks

Mobile ad hoc networks (MANET) are composed of moving wireless hosts which, within range of each other, form wireless networks. For communication to occur between hosts that are not within each others range, routes involving intermediate nodes must be established; however, since the hosts may be in motion, a host that was part of a route may move away from its upstream and downstream partners, thus breaking the route. In this paper, we propose anticipated route maintenance (ARM) protocol with two extensions to route discovery based routing scheme: Extend the route when nodes on a link move apart from each other and they have common neighbor that can be “inserted” in the path, and shrink route when a node discovers that one of its neighbor which is not the next hop is also on the same route several hops later on. By utilizing only local geographic information (now a part of some route finding algorithms), a host can anticipate its neighbors departure and, if other hosts are available, choose a host to bridge the gap, keeping the path connected. We present a distributed algorithm that anticipates route failure and performs preventative route maintenance using location information to increase a route lifespan. The benefits are that this reduces the need to find new routes (which is very expensive) and prevents interruptions in service. As the density of nodes increases, the chance to successfully utilize our route maintenance approach increases, and so does the savings. We have compared the performance of two protocols, pure dynamic source routing (DSR) protocol and DSR with ARM. The simulation results show how ARM improves the functionality of DSR by preventing the links in the route from breaking. Packets delivery ratio could be increased using ARM and achieved approximately 100% improvement. The simulations clarify also how ARM shows a noticeable improvement in dropped packets and links stability over DSR, even though there is more traffic and channel overhead in ARM.

Gigabit optical network interface card using parallel data fiber link for a free-space switched local area network system

We introduce a distributed parallel system, developed under VIVACE program which consists of eight host nodes connected through free-space optically interconnected (FSOI) switch with Terabit bi-section bandwidth. A PCI-based VIVACE optical network interface card (VONIC) with 12Gbps parallel data fiber link is the interface between the host and the FSOI switch. This paper describes the second generation VONIC and related testing results. At the center of the VIVACE system is a switch multi chip-module (MCM) consisting of sixteen CMOS ASICs integrated with two-dimensional GaAs VCSEL and photodetector arrays that are linked via free space using an opto-mechanical system.

Design of a Next Generation High-Speed Data Bus

Future space and military applications, such as, NASA space exploration missions, will require high-bandwidth but dependable avionics architectures for on-board mission-critical processing and aggregate information exchange among subsystems. This paper is to present a design process that we at Honeywell Labs have used to design next generation high-speed avionics with open system architecture. The process begins with review of prior arts and collection of voice of customers. Candidate open source technologies are then identifled by a Six-Sigma based study, followed by a failure mode and efiect analysis to select and deflne a proof-of-concept system architecture. The proof-of-concept architecture is evaluated, validated, and reflned using OpNet Modeler simulations. In the context of this paper, we use IEEE-1394b based avionics design as an example to describe this process.

Design of a multigigabit optical network interface card

High-speed optical data links enable local area networks (LANs) that operate at data rates above 10 Gb/s. Various network, protocol and switch architectures have been proposed that use these links. The optical network interface card (ONIC) is an important component for demonstrating efficient application of these architectures. In this paper, we describe the design of a programmable ONIC that interfaces a 12-channel gigabit parallel optical link module with a 64-bit/66-MHz PCI computer bus. Hardware programmability (using FPGAs) enables the ONIC to efficiently implement different communication protocols. For hardware testing, the ONIC hardware was programmed for bit error rate (BER) analysis. In continuous operation at 8 Gb/s for 30 days through a 1-m fiber, no errors occured. For application testing, a custom ONIC software driver was developed. We used this driver to demonstrate message passing between applications running on two ONIC-equipped servers. The ONIC design provides a low-cost solution that can be readily adapted for application and device specific requirements. The use of ONIC in a free-space optical switch system is described here.