Jeremy Ekman

Description and evaluation of the FAST-Net smart pixel-based optical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors.

The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays of monolithically integrated vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs) were designed, fabricated, and incorporated into a folded optical system that links a 10 cm x 10 cm multichip smart pixel plane to itself in a global point-to-point pattern. The optical system effects a fully connected network in which each chip is connected to all others with a multichannel bidirectional data path. VCSELs and detectors are arranged in clusters on the chips with an interelement spacing of 140 microm. Calculations based on measurements of resolution and registration tolerances showed that the square 50-microm detector in a typical interchip link captures approximately 85% of incident light from its associated VCSEL. The measured optical transmission efficiency was 38%, with the losses primarily due to reflections at the surfaces of the multielement lenses, which were not antireflection coated for the VCSEL wavelength. The overall efficiency for this demonstration is therefore 32%. With the measured optical confinement, an optical system that is optimized for transmission at the VCSEL wavelength will achieve an overall efficiency of greater than 80%. These results suggest that, as high-density VCSEL-based smart pixel technology matures, the FAST-Net optical interconnection concept will provide a low-loss, compact, global interconnection approach for high bisection-bandwidth multiprocessor applications in switching, signal processing, and image processing.

FAST-Net optical interconnection prototype demonstration program

This paper reports progress toward the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The prototype system incorporates 2D arrays of monolithically integrated high- bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 micrometers . The circular VCSEL elements have a diameter of 10 micrometers and the square PDs have an active region that is 50 micrometers wide. These arrays are packaged and mounted on circuit boards along with the CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.

FAST-Net optical interconnection prototype demonstration

Highly interconnected multiprocessor systems are now performance limited by the backplane interconnection bottleneck associated with planar interconnection technologies. Smart pixel throughput capabilities are projected to exceed I Thitls/cm2 [1] and offer the promise of overcoming the bottlenecks of planar technologies for many types of interconnection-limited multiprocessor problems. Systems that use smart pixel-based free space optical interconnects (FSOI) provide two general dense interconnection capabilities: intelligent parallel data transfer and intelligent parallel data interchange. Optical imaging provides a high throughput approach to linking smart pixel planes for data transfer. In this case the high 110 density of smart pixels may provide a power consumption and size advantage over electronics [2,3]. For data interchange, FSOI provides the additional ability to perform the data partitioning and interleaving useful in space variant link interconnection patterns like the perfect shuffle (PS) [41,which are inherently difficult to implement in planar interconnection technologies. Such patterns are characterized by high BSBW [51. In multi-processor architecture design, there is a direct trade-off between minimum BSBW and latency in a network. It is therefore generally desirable to implement networks with the largest minimum BSBW that can be practically achieved to solve a given problem. The ability of optical elements to interconnect large arrays in space-variant patterns, without crosstalk in the medium, suggests that FSOI techniques are particularly promising for problems with high BSBW. For problems with greater than 1 ThitJsec BSBW (i.e., greater than the capabilities of a single chip) free space optical interconnects have a marked advantage [6,71. Therefore, globally interconnected multi-chip smart pixel based architectures have the potential to reap the full benefits of FSOI. This paper describes the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under the Free-space Accelerator for Switching Terabit tworks (FAST-Net) project, sponsored by the U.S. Defense Advanced Research Projects Agency. The prototype system incorporates 2-D arrays of monolithically integrated high-bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect of the FAST-Net concept is that all smart pixels are distributed across a single multi-chip plane. This plane is connected to itself via an optical system that consists of an array of matched lenses (one for each smart pixel chip position) and a mirror. The optical interconnect system implements a global point-to-point shuffle pattern. The interleaved 2-D arrays of VCSELs and PDs in the prototype are arranged on a clustered self-similar grid pattern with a closest element pitch of 100 tm. The circular VCSEL elements have a diameter of 10 pm and the square PDs have an active region that is 50 jim wide. These arrays are packaged and mounted on printed circuit boards along with CMOS driver, receiver, and FPGA controller chips. Micro-positioning mounts are used to effect alignment that is consistent with current MCM chip placement accuracy. Shuffled optical data links between the multiple ICs have been demonstrated in preliminary evaluation of this system. These results suggest that a multi-Terabit optically interconnected MCM module is feasible.

Automated design of ICs with area-distributed I/O pads

We present a methodology that incorporates Epoch and Eggo CAD tools into the IC design flow for area-pad implementation. This method includes creation of an area-pad package description, inclusion of a cell library, building an HDL description netlist of the design that includes area-pads, and execution of the place and route tools.

Application of networking concepts to optoelectronic multiprocessor architectures

This paper describes an approach to creating highspeed multiprocessor architectures involving free-space optical interconnects using knowledge gained from the analysis of traditional network topologies. Development of an architectural specification through identification of the components of a functional description and mapping them to an appropriate network model is presented. By applying these techniques, the designer has the advantage of field tested solutions to the problems that occur in the development of complex, hybrid, hierarchical, optoelectronic multiprocessor architectures, and protocols.

Automated design of integrated circuits with area-distributed input–output pads

We present a method for automating the creation of complementary-metal-oxide-semiconductor (CMOS) integrated circuits that successfully utilizes a large number of area-distributed pads for input-output communication. This method uses Duet Technologies epoch computer-aided-design tool for automated placement and routing of CMOS circuitry, given a schematic netlist as an input. The novelty of this approach is that it uses Duet Technologies eggo program to place and route area-pad signals. To verify this methodology, it is applied to the design of a digital signal-processing circuit, with 200 optical area-pad input-outputs and 44 perimeter-pad input-outputs, that is being fabricated with Bell Labs 1997 CMOS-multiple-quantum-well foundry. The layout results are as good as or better than the results obtained by manual layout.

Programmable network interface for parallel optical data links

Summary form only given. The development of new, multi-gigabit computer communication protocols (such as INFINIBAND) is underway to meet the increasing demand for bandwidth in computing and networking. The aim of our research project is to demonstrate a free-space optical switch fabric together with appropriate network interfaces (using parallel optical data links). Using optical interconnects our hardware can meet the tremendous throughput requirements of these emerging protocols.

Power efficient parallel optical communication links

The development of power efficient parallel optical communication links by using end-to-end power negotiation algorithm in conjunction with a robust and low latency line code is presented.

Corrections to "description and evaluation of the fast-net smart pixel-based optical interconnection prototype"

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.