Brian Welch

Monolithically integrated high-speed CMOS photonic transceivers

We demonstrate monolithically integrated 4×10 Gb/s WDM transceivers built in a production 130 nm SOI CMOS process. Only light sources are external to the chip. 40 Gb/s error-free, bidirectional transmission is demonstrated.

An ultra low power CMOS photonics technology platform for H/S optoelectronic transceivers at less than

We have demonstrated a CMOS Optoelectronic technology platform, using a 650mW 4×10-Gb/s 0.13 μm silicon-on-insulator integrated transceiver chip, co-packaged with an externally modulated laser, to enable high density data interconnects at <

1 per Gbps

1 per Gbps.

A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13μm CMOS Silicon-on-Insulator Technology

We have demonstrated a 40-Gb/s optoelectronic transceiver in a quad small form-factor pluggable (QSFP) module. Each module includes a 4xlO-Gb/s, 0.13 μm CMOS silicon-on-insulator integrated optoelectronic transceiver chip co-packaged with a single, externally modulated CW laser.

25 Gb/s silicon photonic transceivers

We report on the demonstration of an integrated 4×25 Gb/s parallel optical transceiver built in Luxteras CMOS photonics platform, and discuss how we can scale this platform to even higher data rates.

Monolithic Integration of Photonic and Electronic Circuits in a CMOS Process

We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.

Scaling CMOS photonics transceivers beyond 100 Gb/s

We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher speeds and channel counts.

Advantages of CMOS photonics for future transceiver applications

The advantages of CMOS photonics for next generation transceiver applications are outlined in terms of raw bandwidth, channel capacity, reach, power, cost, link performance and reliability. The advantages for future integration with host chips area also discussed.

Demonstration of first WDM CMOS photonics transceiver with monolithically integrated photo-detectors

For the first time we demonstrate a fully self-contained photonic transceiver system on a single die with monolithically integrated Ge photo-detectors. The transceiver allows error-free bidirectional 4times10 Gb/s WDM transmission using a single CMOS die at each end of the link.

Silicon photonic integrated circuits

This paper reviews the CMOS photonics technology developed and commercialized by Luxtera. IC design and CMOS integration methodologies are highlighted and the performance of Luxteras newest 4×14Gbps and 4×25Gbps transceiver chips is discussed.