Brima Ibrahim

A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.

A dual mode 802.11b/Bluetooth radio in 0.35/spl mu/m CMOS

A dual-mode CMOS 2.4GHz transceiver consumes 65mA in RX and 78mA in TX from a 3V supply. The receiver achieves a typical sensitivity of -88dBm at 11Mb/s for 802.11b, and -83dBm for Bluetooth mode. The receiver minimum IIP3 is -8dBm, and the transmitter delivers a nominal output power of 0dBm, with a power control range of 20dB in 2dB steps.

An IP2 Improvement Technique for Zero-IF Down-Converters

An IP2 calibration circuit to improve the 2nd-order nonlinearity of mixers in zero or low-IF receivers is presented. The circuit allows the mixers to be optimized independently, and has negligible impact on receiver noise figure, area, and power consumption. A prototype transceiver including the calibration circuitry in 0.13mum CMOS is fabricated. An average IIP2 improvement of 18dB is measured

A 4GHz Fractional-N synthesizer for IEEE 802.11a

Phase noise of the Fractional-N synthesizer depends critically on the linearity of its building blocks. In this research, new design methods are shown to directly improve its linearity. This includes a new re-timing scheme that effectively reduces phase noise for multi-modulus dividers. Further reductions in phase noise result from introduction of a high linearity CMOS charge pump. Measurement results verify the concept and demonstrate low phase noise performance at 4GHz.

A Single-Chip Bluetooth EDR Device in 0.13μm CMOS

A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, a low-IF receiver and direct-conversion transmitter architecture. It is implemented in a 0.13mum CMOS process and occupies 11.8mm2. Sensitivity for 1, 2 and 3Mb/s rates is -88, -90, and -84dBm and transmitter differential EVM is 5.5% rms.

A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS

This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into a single CMOS chip. Compared to the published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves a superior receive and transmit performance, and yet has up to 2x lower receive power consumption, a key requirement in cellular applications.

An IF FSK demodulator for Bluetooth in 0.35 /spl mu/m CMOS

An FSK demodulator intended for use in Bluetooth is implemented in a 0.35 /spl mu/m CMOS process. The entire demodulator, integrated as a part of a low-IF receiver with 2 MHz intermediate frequency, consumes 3 mA from 2.7 V supply. The required signal-to-noise ratio (SNR) for 0.1% bit error rate (BER) is about 18 dB.

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.

Transmitter development for cellular integrated circuits

This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and the challenges in practical implementations. Then it presents a transmitter as part of a fully integrated transceiver for GSM/GPRS/EDGE.