Ghavam G. Shahidi

Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET

In this work device design of DTMOS and its parasitic components are studied by experiments and simulations. The gate and the body are tied at the side of the device. Similar gate-body tie can also be accomplished in bulk substrate using multiple-well technology. For a circuit whose speed is predominately determined by wiring capacitances, DTMOS can greatly enhance performance by engineering the vertical doping profiles to scale the depletion width. When the circuit speed is dominated by device capacitances, lateral doping engineering is important to reduce Cbs and Cbd in order to obtain performance improvements, especially in certain logic circuits where Miller effect is important.

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L/sub eff/ below 0.2 /spl mu/m.