Venky Sundaram

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Through-package-via formation and metallization of glass interposers

Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias

This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.

Trend from ICs to 3D ICs to 3D systems

Moores Law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15-40 μm in diameter) in 30-μm thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 μm) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 μm at 27-μm pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss <;0.15 dB at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

Simultaneous switching noise suppression for high speed systems using embedded decoupling

High performance computing systems are driving towards higher clock speeds, more switching circuits, and lower operating voltages. Simultaneous switching noise (SSN) will greatly affect signal integrity in such complex future mixed signal systems. It has been reported that in addition to inductance effects, power plane bounce also becomes a critical factor for packages containing many power and ground vias in parallel. Discrete surface mount capacitors are currently being used by designers to suppress noise. As part of the System on a Package (SOP) concept being developed at the Packaging Research Center (PRC), Georgia Tech, a test vehicle to demonstrate the suppression of SSN using embedded decoupling capacitors is being implemented. This test vehicle uses thin film sequential buildup technology on a low-cost organic platform incorporating polymer-ceramic nanocomposite dielectrics. The design rules for the test vehicle were developed using SOP substrate materials and processes; furthermore, Ansoft along with Matlab were used to model the microstrip transmission lines. The layout was done using Cadence Advanced Package Designer (APD) and output into Gerber format for fabrication. The current test vehicle uses a 300 mm /spl times/300 mm high T/sub g/ FR-5 base substrate with four metal layers on each side. Photoimageable epoxy dry films of 25 /spl mu/m and 75 /spl mu/m thickness were used as the low k (3.4-3.9) sequential build-up dielectric. A novel photoimageable polymer ceramic nanocomposite material developed at the PRC was used for the high k (25-50) thin films. Low cost materials and large area processes were used for the substrate fabrication including dry film printed wiring board (PWB) photoresists, vacuum lamination and spin/meniscus coating for dielectric deposition, full-field UV lithography, and electroless and electrolytic copper metallization. Simulations confirm that the SSN will be suppressed by a factor often when using the high k material as the capacitor dielectric. This paper presents the design, fabrication and validation of embedded decoupling for SOP technology.

Next-generation microvia and global wiring technologies for SOP

As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-/spl mu/m area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 /spl mu/m diameter and lines and spaces of 25 /spl mu/m. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for micro via wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 /spl mu/m and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.

Chip-last Embedded Active for System-On-Package (SOP)

Embedded active technology, in which thinned active chips are directly buried into a core or high-density-interconnect layers, is gaining more interest for ultra-miniaturization, increased functionality and better performance of SOP (system-on-package). In this study, chip-last embedded active concept is proposed to address some of process and reliability issues that current chip-first and chip-middle embedded active approaches have. The detailed process development for the first prototype of chip-last embedded active is described in this paper.

Chip-last embedded actives and passives in thin organic package for 1–110 GHz multi-band applications

This paper presents for the first time a novel manufacturing-compatible organic substrate and interconnect technology using ultra-thin chip-last embedded active and passive components for digital, analog, MEMS, RF, microwave and millimeter wave applications. The architecture of the platform consists of a low-CTE thin core and minimum number of thin build up organic dielectric and conductive layers. This organic substrate is based on a new generation of low-loss and thermally-stable thermosetting polymers (RXP-1 and RXP-4). Unlike LCP- and Teflon-based materials, the RXP material system is fully compatible with conventional FR-4 manufacturing processes. Ultra-thin silicon test die (55µm thick) has been embedded in a 60µm deep cavity with a 6-metal layer RXP substrate and a total thickness of 0.22mm. The embedded IC is interconnected to the substrate by ultra-fine pitch Cu-to-Cu bonding with polymer adhesives. This novel interconnection process performed at 180°C, has passed 1,000 thermal shock cycles in reliability testing. Because of manufacturing process simplicity and unparalleled set of benefits, the chip-last technology described in this paper provides the benefits of chip-first without its disadvantages and thus enables highly miniaturized, multi-band, high performance 3D modules by stacking embedded 3D ICs or packages with embedded actives, passives and MEMS devices.