Ryuta Furuya

Design, Modeling, Fabrication and Characterization of 2–5-

This paper presents the latest advances in extending semiadditive process (SAP) methods to 2-5 μm lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20-μm bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below 5 μm. This paper reports on the extension of panel scale and lower cost SAPs to achieve less than 5 μm lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2-μm lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to 5.5 μm at 15-μm signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were 0.024 dB/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass interposer was 0.7 dB at 10 GHz and matched well to the simulated values.

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High-density packages and 2.5D interposers require 2μm trace widths and gaps, and less than 10μm ultra-small microvias to achieve 20-40μm I/O pitch interconnections. Silicon interposers with through-silicon-vias (TSVs) have been used for such ultra-high density interconnections between logic and memory chips with sub-micron multi-layer copper wiring. However, the high cost of silicon interposers coming from back end of line (BEOL) processes have limited their applicability to mobile systems like smart phones and wearables. Glass and organic interposers have been investigated as a lower cost solution coming from large panel processes and dry film lithography for semi-additive copper metallization. However, achieving high wiring density with low-cost package substrate processes remains a challenge. This paper presents the first demonstration of high resolution photo-lithography processes to achieve 2μm copper line widths and 5-10μm microvias with panel-based processes using newly developed large field projection lithography tools and advanced dry film photoresists. A two-metal layer redistribution layer (RDL) structure integrating 2μm line and space wiring and less than 10μm ultra-small microvias was demonstrated on ultra-thin glass and organic substrates.

Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers

This paper describes the demonstration of 10-μm diameter interlayer vias with 3.5-μm wide re-distribution layer copper wiring in a unique dry-film polymer dielectric, ZEONIF ZS100 (ZS100), suitable for panel-based high-density organic and glass interposers. The uniqueness of polymer dielectric includes low dielectric constant, low dielectric loss, low moisture uptake, and low surface roughness. The dry-film polymer dielectric was laminated on thin and low coefficient of thermal expansion organic or glass cores using double-side vacuum lamination processes. The ultrasmall microvias were drilled with 248-nm KrF excimer laser. Metallization by electroless and electrolytic copper plating successfully achieved formation of fully filled vias and copper traces simultaneously without any chemical-mechanical polishing. The processes demonstrated in this paper enable interposers with much finer bump pitch than current organic package technology. In addition, the processes can be scaled to large panels leading to lower cost than the previous work in fine pitch Si interposers fabricated through back-endof-line wafer processes.

Demonstration of 2µm RDL wiring using dry film photoresists and 5µm RDL via by projection lithography for low-cost 2.5D panel-based glass and organic interposers

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

Demonstration of 10-

In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm glass interposers with 300 um core thickness can be realized by utilizing semi additive process. Finally, 10mm × 10m dies with daisy chains can be successfully bonded to 25mm × 30mm glass interposer with 6 metal lines using copper microbumps with SnAg solder caps.

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This paper presents the first demonstration of a novel fiber coupling structure that enables low-loss and low-cost fiber coupling in an ultra-miniaturized 3D glass photonic interposer. The novel 3D coupling structure consists of a tapered optical waveguide with an integrated lensed turning mirror on one end and a cylindrical lens on the other end, in a 150 μm glass substrate. The lens waveguide and turning mirror provide coupling loss of <;0.5 dB and 90% tolerance of 2 μm for out-of-plane coupling between a Photonic Integrated Circuit and a single-mode fiber. The lens waveguide is fabricated using planar lithography to reduce overall cost. In addition, precision U-grooves in glass are employed to allow for a coefficient of thermal expansion matched interface between the fiber and the substrate, thus enabling low-cost passive alignment.

m Microvias in Thin Dry-Film Polymer Dielectrics for High-Density Interposers

This paper presents a novel, high density, and large panel compatible thin film redistribution layer (RDL) process, with 2 μm diameter microvias and 2 μm fine line and space Cu traces on a thin glass panel using a photo-lithographic embedded trench approach. Newly developed thin dry film photosensitive polymer dielectrics were used for the fabrication of photo-vias and photo-trenches by conventional i-line 365 nm UV lithography in this work. Smallest feature dimensions of 1.5 μm trace widths and spaces were achieved by using liquid photosensitive polymer dielectrics. Such a high density, panel scale RDL is applicable to both high performance 2.5D interposers and high-density fan-out packages. The photo embedded trench process retains the cost advantages of the conventional semi-additive process (SAP) while overcoming its scaling challenges. The photo embedded trenches integrated with photovias using a thin, dry film photodielectric have higher resolution, precise via registration, and lower cost compared to the existing embedded trench methods. A dual-layer photo trench process was proposed and developed to address the challenges of copper plating uniformity in vias, pads and trenches. A test coupon consisting of six area array test structures with via diameters ranging from 2 to 5 μm at 20 μm pitch and lines and spaces of 2.5, 3, and 5 μm were designed and demonstrated on a 100 μm thin panel glass substrate. The 5 μm wide features was designed to capture vias within the trenches for a padless multi-layer RDL structure, with via diameters close to the line width enabled by the improved dimensional stability of glass compared to organic laminates. A new type of configuration, via-in-trench, with higher routing capacity than dog-bone or via-in-pad structures, was proposed and demonstrated on thin glass panels based on the photo embedded trench technology. Routing structures of line-space-via-trench (L, S, Via, T) of 3, 3, 3, 5 and 2.5, 2.5, 2, 2.5 μm on thin glass substrates were demonstrated without the use of via capture pads.

Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost

This paper describes the first demonstration of 8-10μm diameter micro-vias at 20μm pitch in ultra-thin dry-film polymer dielectrics to achieve high-density and low-cost redistribution layers (RDL) on panel-based glass and organic interposers. A polymer dielectric dry-film, ZEONIF ZS100, at 10μm thickness was double side laminated on thin and low CTE glass and organic substrates. Micro-via arrays at 20μm pitch were formed by 248nm KrF excimer laser ablation using mask projection scanning, and metallized by a semi-additive process (SAP) using electroless and electrolytic copper plating, with no chemical-mechanical polishing to form fully filled via structures. Fully-filled micro-vias at 20um were achieved using processes scalable to large panels for low-cost and high-density 2.5D and 3D interposers.

Design and demonstration of large 2.5D glass interposer for high bandwidth applications

This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 μm lines and spaces with 4-5 μm diameter photo-vias for multiple re-distribution layers (RDL) at 20 μm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth need with lowest power consumption has enabled the application of 2.5D interposers for high density chip-to-chip interconnections. Silicon interposers with through-silicon-vias (TSVs) are capable of ultra-high density wiring between logic and memory chips, but use back end of line (BEOL) dual damascene processes, requiring chemical mechanical polishing (CMP), leading to high process cost, which limits their expansion into lower cost and higher volume applications. On the other hand, organic substrates processed on large panels have large capture pads for via landing due to their poor dimensional stability, limiting the bump pitch scaling at chip level. Glass interposers have been proposed to address the limitations of both silicon interposers and organic substrates in recent years. This paper reports on research to extend low cost and large panel semi-additive processes (SAP) to below 5um lines and vias. To achieve this, high resolution lithography processes combined with photosensitive dry film polymer dielectrics were optimized to form fine patterns and ultra-small micro-vias. A major challenge for multilayer RDL is the non co-planarity of copper electroplating, and a new cost-effective copper surface planarization process was proposed and evaluated for surface co-planarity improvement, leading to better yields for multi-layer RDL fabrication.

Design and Demonstration of Micro-Mirrors and Lenses for Low Loss and Low Cost Single-Mode Fiber Coupling in 3D Glass Photonic Interposers

This paper demonstrates, for the first time, a high density, low cost redistribution layer (RDL) stack-up using a novel, ultra-thin dry film photosensitive dielectric material for panel scale 2.5D glass interposers and fan-out packages. The salient features of this semi-additive process based RDL demonstrator include: (1) A two metal layer RDL structure with integration of 5 μm microvias at 20 μm pitch and escape routing of 2 μm Cu traces at 4 μm pitch. (2) 5 μm microvias fabricated using low cost i-line 365 nm UV photolithography process in ultra-thin 5 μm dry film photosensitive dielectric. The new photosensitive dielectrics, IF4605 (5 μm thick) and IF4610 (10 μm thick) in discussion, are primarily epoxy polymer based dry films. Epoxy resin is the standard polymer dielectric used in conventional package substrates today. Also, IF films have low dielectric constant and low curing temperatures as is the case with conventional epoxy dielectrics. This paper will demonstrate a multi-layer RDL stack with IF dry film for 20 μm I/O pitch interposers or fan-out packages. The panel based sputtering approach will be used to deposit Ti and Cu as the barrier and seed layers respectively. This also ensures high yield and reliability of the fine pitch Cu traces. The reliability of fine pitch Cu photovias are currently being evaluated for thermal cycling tests (TCT). Initial results are presented in the paper.