Vijay Sukumaran

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Through-package-via formation and metallization of glass interposers

Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias

This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.

Trend from ICs to 3D ICs to 3D systems

Moores Law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15-40 μm in diameter) in 30-μm thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 μm) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 μm at 27-μm pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss <;0.15 dB at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications

Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10–30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred to as interposer approach using ultra-thin glass or silicon with ultra-high I/O density interposers, which does not require TSVs in the logic IC in the 3D stack. This paper presents a comparative study, based on electrical modeling of the logic-to-memory signal path, in various current and emerging package configurations for use in smart mobile devices. Frequency and time domain analysis for each of these scenarios is performed using both chip and package-level models with varying interconnection dimensions. Simulated eye diagrams for the complete data paths in the thin glass interposer approach demonstrated more than 3 Gbps/pin data rate, similar to 3D ICs.

Design and fabrication of bandpass filters in glass interposer with through-package-vias (TPV)

This paper presents the integration of WLAN (2.4 and 5GHz) bandpass filters in glass interposer using through-package vias. The filters include novel embedded passive components such as stitched capacitors with reduced shunt parasitics and via-based inductors that provide area reduction. The filters designed for 2.4 GHz showed an insertion loss of less than 2dB and better than 15dB return loss, while the 5GHz filters showed an insertion loss of less than 1dB with better than 20dB return loss. Stop-band rejection of over 35dB was observed at 2.2 GHz on the 2.4 GHz bandpass filters. The measured results showed good agreement with the simulated values and indicated that the performance on glass interposer closely matches the performance of the more expensive high resistivity silicon with similar properties.

Thermomechanical and electrochemical reliability of fine-pitch through-package-copper vias (TPV) in thin glass interposers and packages

This paper reports reliability of copper-plated through-package-vias (TPVs) in glass interposer by modeling and experimental validation using accelerated life tests. In this paper, both thermomechanical reliability and electrochemical reliability of fine-pitch TPVs in glass interposer were investigated. Thermomechanical reliability was investigated by developing finite element models to calculate the thermomechanical stresses and strains inside TPVs during thermal cycling tests with several glass and polymer liner combinations. Fatigue lifetime of TPVs in glass is predicted based on these simulation results and then validated using experiments. Test samples with daisy chains of TPVs are fabricated with different glass and polymer material combinations and subjected to accelerated temperature cycling tests to assess the thermomechanical reliability of TPVs in glass interposer. Resistance of each daisy chain is monitored using 4-point probe during cycling. It is observed that majority of test samples passed 1000 thermal cycles without any significant changes in electrical resistance. Cross-sectioning of TPV daisy chains that showed significant changes in resistance, revealed that failures were related to defects induced during copper plating in TPV side walls. Electrochemical migration reliability of TPVs in glass was investigated to study conductive anodic filament (CAF) resistance of glass at very small via spacing. Test samples with different material combinations were subjected to biased and highly accelerated stress temperature-humidity test (HAST) to assess electrochemical migration reliability of TPVs. After biased-HAST for 100 hours at 130°C, 85% relative humidity (RH) and 5 V DC, no CAF failures were detected in either of the two material combinations, indicating good insulation reliability under high temperature and humidity conditions.

Ultra-miniaturized and surface-mountable glass-based 3D IPAC packages for RF modules

This paper demonstrates ultra-miniaturized RF passive components integrated on thin glass substrate with small Through Package Vias (TPVs) to realize 3D Integrated Passive and Actives Component (IPAC) concept. Miniaturization is achieved through; a) ultra-thin glass, b) low-loss thin dielectrics and c) small TPVs. Inductors, capacitors and low pass filters functioning in the frequency range of 0.8 GHz to 5.4 GHz were modeled and fabricated between thin dielectric layers on 100 μm thin glass, and then assembled on PCB through BGA interconnections. The simulated results corroborated well with measured results, providing guidelines for RF module fabrication.

Modeling, design, and fabrication of ultra-high bandwidth 3D Glass Photonics (3DGP) in glass interposers

This paper presents, for the first time, the 3D Glass Photonics (3DGP) technology being developed by Georgia Tech, based on ultra-thin 3D glass interposer [1]. The 3DGP system integrates both optical and electrical interconnects in the same glass substrate using photo-sensitive polymer core, and polymer cladding within an ultra-thin glass substrate. The 3DGP processes are demonstrated using 180 & 100 um thick glass substrates with 30 um diameter via and 8 um wide waveguide structures. The optical vias are used as mode transformer and high-tolerance coupler between fibers and chips. Finite-difference analysis is performed to determine the alignment tolerances of such vias.