Paul E. Dodd

Basic mechanisms and modeling of single-event upset in digital microelectronics

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Radiation Effects in MOS Oxides

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Production and propagation of single-event transients in high-speed digital logic ICs

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Radiation effects in SOI technologies

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

Current and Future Challenges in Radiation Effects on CMOS Electronics

Advances in microelectronics performance and density continue to be fueled by the engine of Moores law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moores law to alternatives to traditional CMOS technologies.

Critical charge concepts for CMOS SRAMs

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

Device simulation of charge collection and single-event upset

In this paper we review the current status of device simulation of ionizing-radiation-induced charge collection and single-event upset (SEU), with an emphasis on significant results of recent years. We present an overview of device-modeling techniques applicable to the SEU problem and the unique challenges this task presents to the device modeler. We examine unloaded simulations of radiation-induced charge collection in simple p/n diodes, SEU in dynamic random access memories (DRAMs), and SEU in static random access memories (SRAMs). We conclude with a few thoughts on future issues likely to confront the SEU device modeler.

Heavy ion-induced digital single-event transients in deep submicron Processes

Single-event transients (SETs) in digital circuits/processes are examined. SETs appear to substantially mitigate traditional SEU static-latch hardening techniques below 0.25 /spl mu/m. The resulting IC error rate for advanced technology node hardened-electronics is dominated by the combinational-logic SET rate.

Precursor ion damage and angular dependence of single event gate rupture in thin oxides

No correlation was observed between single-event gate rupture (SEGR) and precursor damage by heavy-ion irradiation for 7-nm thermal and nitrided oxides. Precursor ion damage at biases below SEGR threshold for fluence variations over three orders of magnitude had no significant effect on SEGR thresholds. These data support a true single ion model for SEGR. A physical model based on the concept of a conducting pipe is developed that explains the empirical equation for the linear dependence of inverse critical field to rupture with LET. This model also explains the dependence of critical voltage on angle of incidence. As the oxide thickness approaches the diameter of the conducting pipe, the angular dependence of the critical voltage disappears. A model fit to the data suggests a central core diameter of 6 and 8 nm for conducting pipes induced in MOS oxides by Br and Au ions, respectively. The buildup of precursor ion damage in the oxides depends on ion species and bias during irradiation, but is not consistent with the accumulation of total ionizing dose damage. Some 5-nm oxides exhibited the characteristic high leakage current of SEGR; however, most 5-nm devices showed only soft breakdown during heavy ion exposure with electric fields up to 12 MV/cm.