J.R. Schwank

Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices

We have identified several features of the 1/f noise and radiation response of metal‐oxide‐semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface tr...

Device modeling of ferroelectric capacitors

A physically based methodology is developed for modeling the behavior of electrical circuits containing nonideal ferroelectric capacitors. The methodology is illustrated by modeling the discrete ferroelectric capacitor as a stacked dielectric structure, with switching ferroelectric and nonswitching dielectric layers. Electrical properties of a modified Sawyer–Tower circuit are predicted by the model. Distortions of hysteresis loops due to resistive losses as a function of input signal frequency are accurately predicted by the model. The effect of signal amplitude variations predicted by the model also agree with experimental data. The model is used as a diagnostic tool to demonstrate that cycling degradation, at least for the sample investigated, cannot be modeled by the formation of nonswitching dielectric layer(s) or the formation of conductive regions near the electrodes, but is consistent with a spatially uniform reduction in the number of switching dipoles.

Radiation effects in SOI technologies

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Modeling ferroelectric capacitor switching with asymmetric nonperiodic input signals and arbitrary initial conditions

The switching behavior of ferroelectric capacitors experiencing arbitrary time‐dependent electric fields and arbitrary initial conditions is investigated both theoretically and experimentally. A general approach for modeling incomplete dipole switching in ferroelectric capacitors is used to derive equations describing the electrical behavior of a simple characterization circuit with arbitrary initial conditions and arbitrary time‐dependent applied voltages. The equations include four experimentally determined parameters: the remanent and spontaneous polarizations, the coercive field, and the ferroelectric dielectric constant. Once these model parameters are determined from a single high‐frequency sinusoidal hysteresis loop, model predictions are made with no adjustable parameters. The circuit behavior for both sinusoidal and trapezoidal input signals is computed, including asymmetric and nonperiodic signals as well as several different initial conditions. The accuracy of the model predictions is quantitat...

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

Current and Future Challenges in Radiation Effects on CMOS Electronics

Advances in microelectronics performance and density continue to be fueled by the engine of Moores law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moores law to alternatives to traditional CMOS technologies.

Border traps: Issues for MOS radiation response and long-term reliability

Abstract We have performed an extensive study of the effects of border traps (near-interfacial oxide traps that can communicate with the underlying Si over a wide range of time scales) on the response of metal-oxide-semiconductor (MOS) devices to ionizing radiation. Estimates of border-trap densities for several types of MOS devices are obtained by capacitance-voltage (CV) hysteresis, 1 f noise, and combined CV/thermally-stimulated-current methods. A new “dual-transistor border-trap” (DTBT) technique is described in detail which combines conventional threshold-voltage and 1-MHz charge-pumping measurements on n- and p- channel MOS transistors to estimate radiation-induced oxide-, interface-, and border-trap charge densities. Estimates of border-trap charge densities obtained via the DTBT technique agree well with trap densities inferred from other techniques. In some devices, border-trap charge densities (which can be greater than 1012 cm−2 following ionizing radiation exposure) can approach or exceed interface-trap charge densities, emphasizing the need to distinguish border-trap effects from interface-trap effects in models of MOS radiation response and long-term reliability. This appears to be especially critical for MOS devices with ultrathin (less than ∼6 nm) oxides, in which border traps and interface traps likely will be the dominant defect types. Effects of border traps on MOS scattering rates, cryogenic applications, and long-term reliability assessment are also discussed.

Charge yield for cobalt-60 and 10-keV X-ray irradiations of MOS devices

The radiation response of MOS devices exposed to /sup 60/Co and low-energy ( approximately 10 keV) X-ray irradiation is evaluated as a function of electric field during exposure. Improved charge yield estimates are obtained for /sup 60/Co irradiations at fields below 1 MV/cm by matching voltage shifts due to oxide-trap and interface-trap charge to an E/sup -0.55/ electric field dependence. Combining these improved charge yield estimates and calculated dose enhancement factors, the relative response of X-ray to /sup 60/Co irradiations is accurately predicted for oxide electric fields from 0.03 MV/cm to 5.0 MV/cm. The ability to predict the relative response to X-ray to /sup 60/Co irradiations-should speed acceptance of X-ray testers as a hardness assurance tool. >

Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices

The electric field dependence of radiation-induced oxide- and interface-trap charge ( Delta V/sub ot/ and Delta V/sub it/) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (E/sub ox/) from -4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of Delta V/sub ot/ and the saturated value of Delta V/sub it/ for both polysilicon- and metal-gate transistors are shown to follow an approximate E/sup -1/2/ field dependence for E/sub ox/>or=0.4 MV/cm. An E/sup -1/2/ dependence for the saturated value of Delta V/sub it/ was also observed for negative-bias irradiation followed by a constant positive-bias anneal. The E/sup -1/2/ field dependence observed suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO/sub 2/ interface for positive-bias irradiation or near the gate/SiO/sub 2/ interface for negative bias irradiation, though H/sup +/ drift remains the likely rate-limiting step in the process. Based on these results, a hole-trapping/hydrogen transport model-involving hole trapping and subsequent near-interfacial H/sup +/ release, transport, and reaction at the interface-is proposed as a possible explanation of Delta V/sub it/ buildup in these polysilicon- and metal-gate transistors. >

Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 mum to 70nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies