Bruce R. Hancock

CMOS active pixel sensor specific performance effects on star tracker/imager position accuracy

This paper gives the status of theoretical and experimental efforts at JPL in the development of environmentally robust (Radiation Hard and radiation Tolerant), ultra-low power, high performance CMOS active pixel sensor (APS) imagers for start tracker/imager applications. The work explores the effect of imager performance on star position accuracy, specifically examining the performance of JPL designed APS imagers. Accuracy is estimated as a function of star magnitude for a nominal star tracker optical design. Using these APS sensors, which have wide dynamic range and no blooming, simultaneous imaging of widely differing star magnitudes during the same observation is possible. It is shown that prototype Rad Hard APS imagers meet many next generation, star tracker/imager mission performance requirements when operated at reduced temperatures. These imagers also provide excellent performance at cryogenic operating temperatures appropriate to some anticipate flight missions. APS imagers with their high level of integration, on-chip timing and control, ultra-low power, and environmental robustness are excellent candidates for NASAs earth observing, interplanetary and deep space exploration missions.

Multi-megarad (Si) radiation-tolerant integrated CMOS imager

The paper describes the design, operation, and performance of integrated CMOS imagers that withstand multi-megarad(Si) total dose of ionizing radiation. It reports test result from two imagers - one with on-chip integrated timing and control, and the other with a variety of pixel structures for parametrically investigating the effects of radiation ion imager performance. The CMOS Imager has been shown to response only to ionizing radiation, and is able to withstand high proton fluence. Minimal change in imager performance is observed after being subjected to a proton fluence of 1.2 X 1012 protons/cm2. The imager also exhibits minimal change in optical response after being dosed with 1.5 Megarad(Si). The radiation-induced dark current ins small and is well-behaved over the entire dose range. No change in operation bias is needed either for operating the imager at low-temperature or after irradiation. The parametric test chip indicates that the LOCOS region plays a significant role in determining the total-side-hardness of the pixel. Based on test results, most promising pixel structures for imaging under high radiation environments have been identified.

Hardening CMOS imagers: radhard-by-design or radhard-by-foundry

A comparative study between radhard-by-design and radhard-by-foundry approaches for radiation hardening of CMOS imagers is presented. Main mechanisms for performance degradation in CMOS imagers in a radiation environment are identified, and key differences between the radiation effects in CMOS imagers and that in digital logic circuits are explained. Design methodologies for implementation of CMOS imagers operating in a radiation environment are presented. By summarizing the performance results obtained from imagers implemented in both radhard-by-design and radhard-by-foundry approaches, the advantages and shortcomings of both approaches are identified. It is shown that neither approach presents an optimum solution. The paper concludes by discussing an alternate pathway to overcome these limitations and enable the next-generation high-performance radiation-hard CMOS imagers.

Accurate Estimation of Conversion Gain and Quantum Efficiency in CMOS Imagers

We present a new technique for accurate estimation of quantum efficiency, conversion gain, and noise in imagers. The traditional mean-variance method provides an erroneous estimation of these parameters for a non-linear device. Quantum efficiency, estimated by the mean-variance method, changes with the illumination level, a result that is inconsistent with theory. The estimation error can be easily larger than 50%, at mid-level illumination, and results from incorrect modeling of the transfer function. This is corrected by using non-linear estimation methods that force the slope of the photon transfer function to be proportional to the conversion gain. This results in accurate modeling of the signal dependence of the conversion gain, and in turn, accurate estimation of quantum efficiency and noise. By applying both methods to the measured data gathered from the same mega-pixel imager operated under different biasing conditions, it is shown that the non-linear estimation method provides a reliable and accurate estimation of quantum efficiency and noise, while the mean-variance method over-estimates quantum efficiency and under-estimates noise.

Noise sources and noise suppression in CMOS imagers

Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

Next-generation CMOS active pixel sensors for satellite hybrid optical communications/imaging sensor systems

Given the current choices of (1) an ever increasing population of large numbers of satellites in low-earth orbit (LEO) constellations for commercial and military global coverage systems, or (2) the alternative of smaller count geosynchronous satellite system constellations in high-earth (HEO), of higher cost and complexity, a number of commercial communications and military operations satellite systems designers are investigating the potential advantages and issues of operating in the mid-earth orbit altitudes (MEO) (between LEO and HEO). At these MEO altitudes both total dose and displacement damage can be traded against the system advantages of fewer satellites required. With growing demand for higher bandwidth communication for real-time earth observing satellite sensor systems, and NASAs interplanetary and deep space virtual unmanned exploration missions in stressing radiation environments, JPL is developing the next generation of smart sensors to address these new requirements of: low-cost, high bandwidth, miniaturization, ultra low-power and mission environment ruggedness. Radiation hardened/tolerant Active Pixel Sensor CMOS imagers that can be adaptively windowed with low power, on-chip control, timing, digital output and provide data-channel efficient on-chip compression, high bandwidth optical communications links are being designed and investigated to reduce size, weight and cost for common optics/hybrid architectures.

Comparing the low-temperature performance of megapixel NIR InGaAs and HgCdTe imager arrays

We compare a more complete characterization of the low temperature performance of a nominal 1.7um cut-off wavelength 1kx1k InGaAs (lattice-matched to an InP substrate) photodiode array against similar, 2kx2k HgCdTe imagers to assess the suitability of InGaAs FPA technology for scientific imaging applications. The data we present indicate that the low temperature performance of existing InGaAs detector technology is well behaved and comparable to those obtained for state-of-the-art HgCdTe imagers for many space astronomical applications. We also discuss key differences observed between imagers in the two material systems.

Characterization of NIR InGaAs imager arrays for the JDEM SNAP mission concept

We present the results of a study of the performance of InGaAs detectors conducted for the SuperNova Acceleration Probe (SNAP) dark energy mission concept. Low temperature data from a nominal 1.7um cut-off wavelength 1kx1k InGaAs photodiode array, hybridized to a Rockwell H1RG multiplexer suggest that InGaAs detector performance is comparable to those of existing 1.7um cut-off HgCdTe arrays. Advances in 1.7um HgCdTe dark current and noise initiated by the SNAP detector research and development program makes it the baseline detector technology for SNAP. However, the results presented herein suggest that existing InGaAs technology is a suitable alternative for other future astronomy applications.

Advances in ultralow-power highly integrated active pixel sensor CMOS imagers for space and radiation environments

To develop more cost-effective future satellites and spacecraft systems, instruments and avionics are evolving into smaller/lighter-weight and more power efficient modules. NASAs future missions will require that these lighter weight systems have smaller shielding mass margins and operate at cryogenics temperatures in stressing radiation. JPL has been exploring several approaches to improving the radiation performance of CMOS Active Pixel Sensor (APS) imagers for ultra-low power,

Advances in second-generation ultralow-power CMOS active pixel sensor imagers for remote sensing, star tracking, optical comm, and low-cost solar array/antenna boom deployment metrology

JPL has implemented advances in CMOS APS visible sensors well suited for the development of ultra-low power, miniature, highly integrated image sensor systems. Applications for these low cost, modular, high performance camera-on-a-chip sensors include: remote earth and planetary visible science cameras, wireless payload deployment monitors for large mirrors, solar panels, booms and antennas, and FPAs for star trackers, sun sensors and high bandwidth multi-window optical communication beacon tracker. This paper reports on the newest generation of CMOS APS dubbed the Versatile Integrated Digital Imager or VIDI APS camera-on-a-chip. VIDI is an integrated, digital chip-camera with a 512 X 512 format, 12-um pixels, utilizing a single 3.3 V supply, with analog or 10-bit digital output, fabricated on a standard 0.5 um CMOS process. The chip size is 10 mm X 15.5 mm. Features include a simple, all digital five-wire interface, on-chip timing, control, four five-bit DACs for bias generation, and 512 column parallel ADCs, VIDI offers programmable exposure, resolution, data efficient smart area-of-interest windowed high speed readout, no blooming, while continuing to operate with approximately 20 mW of power in the on-state and approximately 40 uW in the sleep state and has a maximum data rate of 20 Mbits/sec.