Bedabrata Pain

256/spl times/256 CMOS active pixel sensor camera-on-a-chip

A CMOS imaging sensor integrates the sensor technology and digital control functions on a single chip. This demonstrates the viability of producing a camera-on-a-chip suitable for commercial, military, and scientific applications. Good imaging performance has been demonstrated with high quantum efficiency, low noise, no lag, no smear and good blooming control. The chip is characterized by random access, simple clocks, low system power, simple power supplies and fast read-out rates. The simple digital interface permits easy restructuring of windows-of-interest and integration times. The measured performance indicates that this technology will become competitive with CCDs in many applications, resulting in enhanced system performance and reduced cost.

A CMOS imager with on-chip variable resolution for light-adaptive imaging

In addition to advantages of lower power and system miniaturization through camera-on-a-chip implementation, the CMOS active pixel image sensor (APS) enables development of smart imagers by integrating custom CMOS signal processing circuits on the focal plane. This CMOS APS imager is capable of enhancing signal to noise ratio (S/N) under low illumination through summation of signals from neighboring pixels. On-chip S/N improvement in CMOS APS is demonstrated by pixel averaging or by pixel binning. Pixel binning is implemented in a CMOS APS primarily designed for frame-transfer. That implementation suffers from extraneous noise pick-up and high-residual fixed-pattern noise (FPN) due to the use of single-ended column integrator. This APS has improved kernel summing circuits implemented in fully-differential topology. The imager performance is improved by greatly reducing FPN and temporal circuit noise. This multi-resolution APS is suited for application in light-level-adaptive imaging.

A snap-shot CMOS active pixel imager for low-noise, high-speed imaging

Design and performance of a 128/spl times/128 snap-shot imager implemented in a standard single-poly CMOS technology is presented. A new pixel design and clocking scheme allow the imager to provide high-quality images without motion artifacts at high shutter speeds (<75 /spl mu/sec, exposure), with low noise (<5 e/sup -/), immeasurable image lag, and excellent blooming protection.

An enhanced-performance CMOS imager with a flushed-reset photodiode pixel

A new front-end for photodiode-based CMOS imagers is presented. Degradation in imaging performance due to conventional hard- and soft-reset of pixels is analyzed. To overcome these limitations, the design and operation of a flushed-reset pixel is described. The flushed-reset pixel combines the best of hard- and soft-reset to simultaneously provide excellent radiometric accuracy, high linearity, no image lag, high saturation level, and reduced read-noise. The new front-end is implemented by changes to the column-circuitry only, leaving the pixel unchanged, preventing degradation of any unrelated imaging performance. It is compatible with large format imager implementation, has minimal impact on the frame-rate, and does not introduce any additional hot-carrier stress in the pixel. Data from a large format (512/sup 2/) imager demonstrates the efficacy of the flushed-reset pixel approach.

Reset noise suppression in two-dimensional CMOS photodiode pixels through column-based feedback-reset

We present a new CMOS photodiode imager pixel with ultralow read noise through on-chip suppression of reset noise via column-based feedback circuitry. In a 0.5 /spl mu/m CMOS process, the pixel occupies only 10/spl times/10 /spl mu/m/sup 2/ area. Data from a 256/sup 2/ CMOS imager indicates imager operation with read noise as low as 6 electrons without employing on- or off-chip correlated double sampling. The noise reduction is achieved without introducing any image lag, and with insignificant reduction in quantum efficiency and full-well.

Development of a Production-Ready, Back-Illuminated CMOS Image Sensor with Small Pixels

A back-illuminated 2 megapixel CMOS sensor utilizing mature wafer manufacturing operations is described. Sensitivity, dark current and other key pixel performance measures are compared against an equivalent conventional sensor. Aspects of the process integration that make the technology manufacturable are described. Simulations that predict the performance of a full color sensor are discussed.

Dynamically reconfigurable vision with high performance CMOS active pixel sensors (APS)

A high-performance computational imager based on integration of CMOS active pixel imager array with on-chip signal processing and control via a new column-parallel architecture is presented. Unlike CCDs and other CMOS imagers, the sensor is capable of providing simultaneous image data from three flexible, partially overlapping, dynamically reconfigurable regions of interest (ROIs) with different spatial resolution over a large field-of-view (FOV) to achieve data-efficient operation with high update rates. The power dissipation depends upon reconfiguration modes, but is small even in the worst case. Unlike conventional computational imagers, the integration of processing circuitry does not trade with radiometric accuracy, nor does it impose any limit to scaling the imager size to larger format and smaller pixels. By eliminating the need for mechanical pointing through floating-fovea support, the dynamically reconfigurable vision sensor (DSRVS) enables a low-power staring vision system. By maximizing system throughput through intelligent data reduction and through real-time programmability, it meets the diverse and conflicting requirements of search, identify and track vision-modes, and represents an efficient platform for high-bandwidth automatic target acquisition and tracking.

A single-chip programmable digital CMOS imager with enhanced low-light detection capability

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, single-chip, digital camera systems. We report at fully digital, programmable, 5-wire, large format (512/spl times/512) camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The chip runs off a single (3.3 V) power supply, consumes only 10 mW, is capable of electronic panning, and produces high quality images with a low noise of <40 e/sup -/, and excellent response linearity down to read noise levels.

A low-power digital camera-on-a-chip implemented in CMOS active pixel approach

The advent of high performance imaging in CMOS technology using active pixel sensors has enabled ultra-low power, miniature, integrated, single-chip camera systems. We report the first fully digital, programmable, 5-wire, large format (512/spl times/512) digital-camera-on-a-chip that integrates the imager array, control logic, ADC, and bias generation on the same chip. The VLSI chip runs off a single (3.3 V) power supply, consumes only 8 mW at video rates, is capable of electronic panning, and produces high quality images with 78 dB dynamic range.

Active pixel sensors for mass spectrometry

Abstract Active pixel sensors (APS) are micro-fabricated CMOS amplifier arrays that are rapidly replacing CCD devices in many electronic imaging applications. Unlike the pixels of a CCD device, the sensing elements of the APS will respond to locally situated electrostatic charge, owing to the amplifier present in each pixel. We have built two small test arrays with microscopic aluminum electrodes integrated onto standard APS readout circuitry for the purpose of detecting low-energy gas-phase ions in mass spectrometers and other analytical instruments. The devices exhibit a near-linear dynamic range greater than four orders of magnitude, and a noise level of less than 100 electrons at room temperature. Data are presented for the response of the APS detectors to small ions in a miniature magnetic sector mass spectrometer and in an atmospheric pressure jet of helium. Data for individual highly-charged electrospray droplets are presented as well. Anticipated improvements suggest that in the near future APS ion detectors will posses noise levels approaching 10 electrons and will have a useful dynamic range over six orders of magnitude.