Bryce D. Horine

Mm-wave phased array antenna and system integration on semi-flex packaging

60GHz technology utilizes world wide exempt 5–9GHz bandwidth to provide multi-gigabit high throughput wireless communication in WPAN and WLAN applications. One of the key challenges to enable 60GHz technology is developing mm-wave phased array antenna design and packaging integration with mm-wave ICs. This paper presents a conformal mm-wave phased array antenna design and packaging integration to provide low loss solution and flexibility for platform integration.

High-Speed Flex-Circuit Chip-to-Chip Interconnects

High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper construction of the flex ribbon is shown to improve the raw bandwidth over standard FR-4 boards by about three times. Active testing results from a 130-nm CMOS test vehicle show the potential of up to two times higher data rates. The next-generation test vehicle with 90-nm CMOS circuits gives improved voltage and timing margins at 20 Gb/s. In an interconnect limited case a channel with 36 in (91.4 cm) of flex runs at 18.2 Gb/s data rate at a bit-error ratio (BER) of better than 10-12. The channel includes two 90-nm CMOS test chips, two organic flip-chip package substrates, and two flex connectors; crosstalk is not included in this experiment. High-speed connector solutions, including results from a ldquosplit socketrdquo assembly test vehicle, are discussed in detail. The characterization of two top-side flex connector prototypes demonstrates their basic durability and good high-frequency performance. Samples survive 100 mating cycles at an average contact resistance of less than 30 mOmega, adequate for high-speed signaling. Measured differential insertion loss is less than 1.5 dB up to 10 GHz and less than 3.5 dB up to 20 GHz. Near-end and far-end crosstalk measurements indicate that the connectors exceed crosstalk specifications.

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm2.

Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards

Techniques for quantifying and minimizing the impact of differential signal phase skew created by the non-homogeneous nature of FR4 PCBs are presented. Experimental results that allow modeling and simulation at multi-Gb/s signaling rates are developed and used to estimate the impact to voltage and timing margins at 5-10 Gb/s as a function of PCB trace length. A design approach for mitigating the impact is discussed, and results from a manufacturability study are used to assess the effectiveness of the approach.

Impact of FR4 dielectric non-uniformity on the performance of multi-Gb/s differential signals

Phase skew in high speed differential signals caused by local spatial variation in dielectric constant is presented. A simple mathematical model that allows estimation of the impact on multi-Gb/s signaling links is developed, along with HSpice models that correlate to frequency domain measurements. Options for mitigating the impacts are also discussed.

Multi-Gbit I/O and interconnect co-design for power efficient links

The co-design of a 10Gb/s 45nm CMOS transceiver and low-loss interconnect for parallel links demonstrates 1.4–2.4pJ/bit I/O power efficiency. A C4 bump pattern with an effective 20∶3 signal to ground ratio is implemented with on-die transmission line routing to escape from the I/O circuitry to the package-die interface. Top-of-the-package connector based (TPCB) interconnects, including high density interconnect (HDI), bonded polyimide (PI) flex, liquid crystal polymer (LCP) flex and micro-twinax cables, are trace length matched in bundles of 9 or 10 I/O lanes to minimize clocking power while requiring only 2-tap TX equalization and 106–373mVpp-diff TX swing. The link measured maximum lane-to-lane phase mismatch ranged from 6ps to 22ps.

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A low-power low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1-2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets. A low-profile connector and cable assembly prototype is developed for these markets, where the link architecture and design are optimized for the channel characteristics. This paper describes a data-rate-scalable 32Gb/s serial link that features a bidirectional transceiver, source-series terminated (SST) 3-tap FFE, a continuous-time linear equalizer (CTLE) with an active inductor, a 6-tap DFE, and clock calibration and adaptation circuitry.

Full Characterization of Substrate Integrated Waveguides from S-Parameter Measurements

A complete methodology to characterize substrate integrated waveguide (SIW) structures from S-parameter measurements is presented. We determined the complex propagation constant, the characteristic impedance of a homogeneous section of waveguide, and the efficiency of different adapters used to launch the signals into the waveguide. After a detailed analysis, it is observed that the most significant losses in an SIW are associated with the adapters since a low insertion loss is presented in a homogeneous section of waveguide

Mm-wave rectangular slot loop antenna array for broad spatial coverage

The multi-Gigahertz worldwide unlicensed band at 60GHz offers many opportunities for developing multi-Gb/s high speed wireless communication. 60GHz technology can enable multiple applications such as extremely fast large file wireless downloading, wireless docking interface for computer, wireless high-definition video streaming, and multi-Gb/s WLAN [1–2]. At 60GHz, phased-array antenna can be compact and provides high directional gain to overcome high propagation loss at 60GHz. In this paper, a planar rectangular slot loop antenna is proposed that provides unique radiation pattern with broad beam pattern tilting toward the side. Other than typical broadside or endfire antenna array, the beam tilted rectangular slot loop antenna array brings flexibility for platform placement while providing broad spatial coverage.

Ultra high-resolution FDTD modeling of a high-performance VLSI package

Integrated Circuits are ever-increasing in complexity while also shrinking in size. Further, ultra mobile devices are ever-increasing in functionality while also becoming more compact in size. The goal of this work is to support these trends by computationally studying electromagnetic compatibility issues both on a device level, as well as on individual component level, since these issues are beginning to dominate the design process of ultra mobile devices. Specifically, as a first step, we are employing an ultra high-resolution full-vector 3-D finite-difference time-domain (FDTD) model having 343 million grid cells to simulate sample ICs. We are using this model to study undesirable induced resonances, coupling, and other electromagnetic phenomena within ICs. In subsequent work, we will be adding additional components to yield an ultra high-resolution 3-D FDTD model of a complete compact portable electronic device.