Howard L. Heck

A Practical Method for Modeling PCB Transmission Lines with Conductor Surface Roughness and Wideband Dielectric Properties

This paper discusses the modeling techniques to account for transmission line high frequency effects, and proposes a method to integrate these techniques into a practical and design-worthy model generation flow. The frequency tabulated transmission line models are capable of predicting wideband dielectric characteristics and high frequency conductor losses due to skin effect and surface roughness. They can be used to accurately model high volume, low cost printed circuit board traces which often have roughened trace surfaces and pronounced frequency variation in dielectric properties. The model accuracy is verified up to 20 GHz in frequency domain, thus suitable for multi-gigabit signaling analysis

Analytical Calculation of the Modes in a Substrate Integrated Waveguide

A first order analytical method is developed to analyze the guided modes in substrate integrated waveguides. The complex propagation constant is derived as a closed expression which is a function of frequency, and geometrical and material parameters. This single equation is able to describe multimode and band gap effects in substrate integrated waveguides. Therefore, the initial design procedure can be greatly simplified by using this analytical model as starting point

A novel trench routing for next-generation high-speed serial buses beyond 10Gbps applications

This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect channel loss budget as stipulated by standard development body e.g. USB-IF specifications. This inventive routing provides huge benefit to original equipment manufacturer (OEM) in term of platform component removal (e.g. USB 3.1 re-timer that costs ∼

USB3.1 transmitter compliance specification definition methodology

1) for high-speed differential links >10Gbps data transfer rates. These cost-adding repeaters would be indispensable under conventional routing for instance microstrip, stripline and dual-stripline for high-speed applications. The PCB trench routing aims to mitigate the existing and future challenges of next-gen multi-Gbps signaling, of which one of the platform length limitations is PCB interconnect loss. In this work, signaling analysis in 10Gbps USB 3.1 and 32Gbps SerDes applications have shown feasibility of yielding significant eye margin improvements i.e. up-to 30% voltage margin improvements, which also translates into ample board design flexibility with extended platform routing length.

Keynotes for ISCE 2012

This paper demonstrates the modeling methodology of the transmitter compliance test and the full link test which is used to develop the 10Gbps USB3.1 compliance specification and the reference equalization.

An implementation of interleaved microstrip motherboard routing in Multi-Gbps I/O channel margin improvement

These keynote speeches discuss the following: “A Day Made of Glass” - A vision for an enabled future: challenges and opportunities Presenter/Title: Zachi Baharav, Ph.D. (Researcher, Corning West Technology Center, Corning Incorporated); 3D Video Coding & Transmission Formats; Evolving Architectures to Support Next Generation Serial Data Rates; Taking your camera from the drawer: Image Sensors Challenges for the Future; Connector Models: Past, Present and Future; Signal Integrity in a Consumer World.

Network Analysis for Digital Engineers

This paper presents an interleaved routing method for motherboard microstrip routing in Multi-Gbps interfaces. The proposed method yields improved channel performance in terms of Eye Height(mV) and Eye Width(ps) margins. Of note is the more prominent improvement in topologies with longer transmission lines. This method enables greater routing flexibility using full microstrip transmission lines with the benefit of improved channel margins at 20 mils inter-pair spacing. More importantly, it allows for the more tightly spaced 15 mils interpair spacing to be utilized without jeopardizing overall channel margins. Ultimately, this translates into a cost saving benefit in line with recent platforms sleek and thin form factor.

Optimized Substrate Integrated Waveguide Bends for Ultra-High Speed Digital Interconnects

This chapter contains sections titled: High-Frequency Voltage and Current Waves Network Theory Properties of Physical S-Parameters References Problems

Advanced Signal Integrity for High-Speed Digital Designs

This paper reports on an experimental and computational study of substrate integrated waveguides (SIW) optimized for use as ultrahigh-speed bandpass wireless digital interconnects. Specifically, a straight and 60deg-bend SIW optimized for narrow transverse dimensions, low loss, low crosstalk, and maximum bandwidth with no multimoding is reported in this paper. Because existing circuit-board technology permits dimensional reductions of SIWs by a factor of 4:1 relative to the ones discussed here, bandpass operation at center frequencies approaching 200 GHz with data rates of 200 Gb/sec appear feasible. These data rates meet or exceed those expected eventually for proposed optical interconnects without requiring the development of a suite of essentially revolutionary silicon photonic technologies