Michael W. Leddige

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs

Contention in performance-critical shared resources affects performance and quality-of-service (QoS) significantly. While this issue has been studied recently in CMP architectures, the same problem exists in SoC architectures where the challenge is even more severe due to the contention of shared resources between programmable cores and fixed-function IP blocks. In the SoC environment, efficient resource sharing and a guarantee of a certain level of QoS are highly desirable. Researchers have proposed different techniques to support QoS, but most existing works focus on only one individual resource. Coordinated management of multiple QoS-aware shared resources remains an open problem. In this paper, we propose a class-of-service based QoS architecture (CoQoS), which can jointly manage three performance-critical resources (cache, NoC, and memory) in a NoC-based SoC platform. We evaluate the interaction between the QoS-aware allocation of shared resources in a trace-driven platform simulator consisting of detailed NoC and cache/memory models. Our simulations show that the class-of-service based approach provides a low-cost flexible solution for SoCs. We show that assigning the same class-of-service to multiple resources is not as effective as tuning the class-of-service of each resource while observing the joint interactions. This demonstrates the importance of overall QoS support and the coordination of QoS-aware shared resources.

High-Speed Flex-Circuit Chip-to-Chip Interconnects

High-speed chip-to-chip interconnect utilizing flex-circuit technology is investigated for extending the lifetime of copper-based system-level channels. Proper construction of the flex ribbon is shown to improve the raw bandwidth over standard FR-4 boards by about three times. Active testing results from a 130-nm CMOS test vehicle show the potential of up to two times higher data rates. The next-generation test vehicle with 90-nm CMOS circuits gives improved voltage and timing margins at 20 Gb/s. In an interconnect limited case a channel with 36 in (91.4 cm) of flex runs at 18.2 Gb/s data rate at a bit-error ratio (BER) of better than 10-12. The channel includes two 90-nm CMOS test chips, two organic flip-chip package substrates, and two flex connectors; crosstalk is not included in this experiment. High-speed connector solutions, including results from a ldquosplit socketrdquo assembly test vehicle, are discussed in detail. The characterization of two top-side flex connector prototypes demonstrates their basic durability and good high-frequency performance. Samples survive 100 mating cycles at an average contact resistance of less than 30 mOmega, adequate for high-speed signaling. Measured differential insertion loss is less than 1.5 dB up to 10 GHz and less than 3.5 dB up to 20 GHz. Near-end and far-end crosstalk measurements indicate that the connectors exceed crosstalk specifications.

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm2.

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A low-power low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1-2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets. A low-profile connector and cable assembly prototype is developed for these markets, where the link architecture and design are optimized for the channel characteristics. This paper describes a data-rate-scalable 32Gb/s serial link that features a bidirectional transceiver, source-series terminated (SST) 3-tap FFE, a continuous-time linear equalizer (CTLE) with an active inductor, a 6-tap DFE, and clock calibration and adaptation circuitry.

Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact

Most power reduction mechanisms for NoC channel buffers rely on on-demand wakeup to transition from a low-power state to the active state. Two drawbacks of on-demand wakeup limit its effectiveness: 1) performance impact caused by wakeup delays, and 2) energy and area cost of sleep circuitry itself. What makes the problem harder to solve is that solutions to either problem tend to exacerbate the other. For example, faster wakeup from a power-gated state requires greater charge/discharge current for the sleep transistors while using nimbler sleep transistors implies long wakeup delays. As a result, power downs have to be conservatively prescribed, missing many power-saving opportunities. We propose Boomerang, a novel power-saving method that overcomes the above drawbacks. Specifically, based on the observation that a response is always preceded by a request, we let the request trigger wakeup of the buffer that is to be used by its response in the (near) future, instead of using on-demand wakeups. Hiding the wakeup delay completely, Boomerang allows us to employ aggressive sleep policies and use low-cost power gating circuits on response buffers.