Bui Thanh Tung

Investigation of low-temperature deposition high-uniformity coverage Parylene-HT as a dielectric layer for 3D interconnection

Polymer low-k materials have been considered in literature to meet the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and reduce cross-talk between the neighboring paths, as well as, lower the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition intelever dielectric in 3D interconnection is investigated and the results are presented. In particular, the diffusivities of Cu in room temperature deposited high-uniformity coverage Parylene-HT at 250 oC and 350 oC are evaluated to be 5.7E-18 cm2/s and 1.3E-16 cm2/s respectively, by dynamic secondary ion mass spectrometry (D-SIMS) technique. In addition, the capability of embedding Parylene-HT in through-Si-via (TSV) fabrication process through the demonstration of 36-μm-diameter 100-μm-depth copper-filled TSVs using Parylene-HT as a liner, are reported.

Fabrication and electrical characterization of Parylene-HT liner bottom-up copper filled through silicon via (TSV)

In this study, Parylene-HT, the newest commercially available parylene with the lowest dielectric constant and highest temperature tolerance within all the series, was investigated as insulation/liner in the application of through-silicon-via (TSV). Bottom-up copper filled TSV with 1 μm Parylene-HT insulator was realized on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and electroplating processes. The fabrication process on the 36 μm diameter TSVs, are reported here, as well as their electrical properties, including DC leakage and capacitance.

Flip-chip bonding alignment accuracy enhancement using self-aligned interconnection elements to realize low-temperature construction of ultrafine-pitch copper bump interconnections

In this paper, the integration accuracy of conventional flipchip bonding is effectively enhanced by means of automatically maintaining the alignment between the chip and substrate during the time that offsets may take place, i.e., bonding conditions applying period. The conventional bonding bump and pad elements have been appropriately modified to construct a concave-convex pair, i.e., self-aligned interconnection elements (SIEs). By this way, the post-bond offsets are determined by the SIEs, aiming at highly reproducible sub-micron range bonding precision. Moreover, because the post-bond offsets are guaranteed by the SIEs, ultrasonic assisted technique can be applied to make reliable bonds at acceptably low temperatures, while still maintaining the integration accuracy. Ultrafine-pitch (i.e. down to 10 μm) copper bump interconnections were realized using the proposed integration approach.

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The accuracy of the bonding process is improved by modifying conventional bump/planar-bonding-pad interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads, i.e., misalignment self-correction elements (MSCEs). Thermosonic flip-chip bonding (FCB) is utilized to form reliable bonds between these MSCEs at acceptable low temperatures. By applying the proposed bonding approach, the demonstration of fine-pitch Cu bump to Au bonding pad interconnects chip stacking has been realized. Microstructure analyses reveal that 15-µm-pitch micro bump joints are fabricated at room temperature.

Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration

In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 μm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm the pin-hole free, high-uniformity, good conformal coverage room temperature deposited Parylene-HT liner, the void- and seam-free filled Cu, as well as the low diffusivity of Cu into Parylene-HT. Excellent insulation function of Parylene-HT liner, i.e., capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm, were also confirmed on the fabricated TSV. As the Parylene-HT deposition and Cu electroplating processes can be implemented at room temperature, the copper filled TSV formation with Parylene-HT insulator investigated in this work is highly compatible with low-temperature 3D integration.

High-precision integration approach based on alignment maintaining flip-chip bonding using cone shaped bump and truncated pyramid pad

In this paper, a high-precision heterogeneous integration approach based on a high alignment accuracy flip-chip bonding using nanoparticle deposition (NpD) cone shaped (CS) bumps and anisotropic wet-etching truncated pyramid (TIP) bonding pads is introduced to precisely control the post-bond position of the bonding chip. Experimental results show that the bonding chip could be confined within sub-micro ranges in all the X-, y- and z-axis. Moreover, reliable bonds with ohmic contacts were realized at 150°C, capable for edge emitting laser (EEL) chip staking applications.

A method enabling height-control of chips for edge-emitting laser stacking

In this paper we present a stacking method that enables the mounting of edge-emitting laser (EEL) devices at compulsory positions for feeding a coupling waveguide at a low temperature, i.e., 110 °C. Bonding laser chips are integrated to an interposer with embedded waveguides using an electrically conductive adhesive (ECA), i.e., silver-filled epoxy resin that relied on the surface tension phenomenon. A simple dispensing technique based on the capillary effect was used to generate adhesive droplets for bonding purposes. The ability to control the bonding height from 3 to 25 µm was demonstrated. While the post-bond in-plane offsets of the bonding EEL chip are determined by the accuracy of the bonder (i.e., within 2 µm range), the bonding height can be engineered, with a deviation within 1 µm, by balancing the external bonding forces with the surface tension of a certain adhesive volume. The reliability of the bond, i.e., bond strength of 106 gf, and heat dissipation function of the ECA, were also validated. The results obtained in this work imply that the use of this low-temperature, height-controllable approach for the stacking of EEL continues to look highly promising.