Jangheon Kim

Optimum operation of asymmetrical-cells-based linear Doherty power Amplifiers-uneven power drive and power matching

We developed a Doherty amplifier with uneven input drive and optimized individual matching for the carrier and peaking cells. In the proposed amplifier, higher input power is delivered to the peaking cell rather than the carrier cell for optimized linear power operation, especially for appropriate load modulation. Both cells are matched differently to further optimize the performance. We analyzed the efficiency of the proposed amplifier as a function of the input drive ratio for the two cells. To interpret the linearity related to the load modulation and harmonic cancellation mechanisms, we simulated the third-order intermodulation amplitude and phase of each cell of the proposed amplifier. For verification, we implemented the asymmetric power amplifier with uneven drive and optimized power matching using Motorolas MRF281SR1 LDMOSFET with a 4-W peak envelope power. For a 2.14-GHz forward-link wireless code-division multiple-access signal, the measured drain efficiency of the amplifier is 40%, and the measured average output power is 33 dBm at an adjacent channel leakage ratio (ACLR) of -35 dBc, while those of the comparable class-AB amplifier are 21% and 30.6 dBm at the same ACLR level, respectively.

The Doherty power amplifier

In this article, we show that the Doherty amplifier is capable of delivering the stringent requirements of the base station power amplifiers. We explain the operation principles, including both linearity and efficiency improvements, and the basic circuit configuration of the amplifier. Advanced design methods to operate across wide bandwidth and improve the linearity are also described. For verification, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal. These results show that the Doherty amplifier is a promising candidate for base station power amplifiers with wide bandwidth, high efficiency, and linearity

Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

Analysis of a Fully Matched Saturated Doherty Amplifier With Excellent Efficiency

A saturated Doherty amplifier based on class-F amplifiers is analyzed in terms of its load modulation behavior, efficiency, and linearity. Simulations included the amplitude ratio and phase difference between the fundamental and third harmonic voltages, the current/voltage waveforms, load lines, and the third-order intermodulation amplitudes/phases of the carrier and peaking amplifiers. The saturated doherty power amplifier was implemented using two Eudyna EGN010MK GaN HEMTs with a 10-W peak envelope power. For a 2.14-GHz forward-fink wideband code-division multiple-access signal, the doherty amplifier delivers an excellent efficiency of 52.4% with an acceptable linearity of -28.3 dBc at an average output power of 36 dBm. Moreover, the amplifier can provide the high linearity performance of -50 dBc using the digital feedback predistortion technique.

High-Efficiency Hybrid EER Transmitter Using Optimized Power Amplifier

This paper describes a new design approach for a power amplifier (PA) of the highly efficient hybrid envelope elimination and restoration (H-EER) transmitter. Since the PA operates mostly at the average power region of the modulation signal, power-added efficiency (PAE) of the PA at the average drain voltage is very important for the overall transmitter PAE. Accordingly, the PA is designed to have a maximum PAE in that region. The performances of the proposed PA and a conventional PA under H-EER operation are evaluated via ADS and MatLab simulations using a behavioral large-signal model of a silicon LDMOSFET, which verifies that the proposed PA has significant advantages for the H-EER transmitter in both PAE and output power. A saturated amplifier, inverse class F, has been implemented using a 5-W peak envelope power LDMOSFET for 3GPP forward-link single-carrier wideband code-division multiple-access at 1 GHz with a peak-to-average power ratio of 9.8 dB. An envelope amplifier is built that has an efficiency of above 68% and peak output voltage of 31 V for an interlock experiment. The overall PAE of the transmitter with a conventional PA is 35.5% at an output power of 29.2 dBm. On the other hand, the transmitter with the proposed PA delivers significantly improved performances: PAE increased by 4% and output power by 2.5 dB. The H-EER transmitter has been linearized by the digital feedback predistortion technique. The measured error vector magnitude is reduced to 1.47% from 6.4%. These results clearly show that the proposed architecture is a good candidate for efficient linear transmitters.

Linear power amplifier based on 3-way Doherty amplifier with predistorter

This paper presents a 3-way Doherty amplifier with predistorter (PD) for a repeater application. It is implemented using three 60 Watts PEP silicon LDMOSFETs and tested using two-tone and one- and two-carrier down-link WCDMA signals. For the two-carrier downlink WCDMA signal, the amplifier provides -49.1 dBc adjacent-channel-leakage-ratio (ACLR) and 10.3% power-added efficiency (PAE) at an output power 40 dBm which is an improvement of 8.5 dBc in linearity and 2% in efficiency compared to a similar class-AB amplifier.

A New Wideband Adaptive Digital Predistortion Technique Employing Feedback Linearization

We develop a new wideband digital feedback predistortion (WDFBPD) technique for modulated signals with wide bandwidths by combining digital feedback predistortion (DFBPD) linearization and memory-effect compensation techniques. For the experiments, a class-AB amplifier using an LDMOSFET with 90-W peak envelope power is employed. The proposed technique is compared with existing DFBPD and memory polynomial (MP) techniques for a 2.14-GHz forward-link WCDMA 2FA signal with 10-MHz carrier spacing. The experimental results show that the new WDFBPD technique has better linearization performance than conventional DFBPD and lower computational complexity than the MP technique.

Efficiency Enhancement of Doherty Amplifier Through Mitigation of the Knee Voltage Effect

This paper presents an approach to maximize the efficiency of a Doherty power amplifier (PA) with the knee voltage effect. Since the carrier PA with , which is the usual matching impedance for a carrier PA at a low power region, does not reach to the saturated operation at the 6-dB back-off power level, the maximum efficiency could not be achieved. However, the carrier amplifier can be driven into the saturation using the load impedance larger than and can deliver the maximum efficiency even under the knee voltage effect. The optimized design for the maximum efficiency at the back-off level is derived. The optimized amplifier is analyzed and simulated in terms of its load modulation behavior, efficiency, and output power, then compared with the conventional Doherty PA. The enhanced performance is demonstrated by the Doherty PA built using CREEs GaN HEMT CGH40045 devices at 2.655 GHz. For worldwide interoperability for microwave access applications with a 7.8-dB peak-to-average power ratio, the proposed PA delivers an efficiency of 49.3% at an output power of 42 dBm with an acceptable linearity of 23.1 dBc. The linearity is improved to 43 dBc by employing a digital feedback predistortion technique, satisfying the system linearity specification.

Highly efficient power amplifier for CDMA base stations using Doherty configuration

We have extended the classical Doherty amplifier to support CDMA base station power amplifiers that require high efficiency and good linearity. At first, we have estimated three transistors, Motorolas MRF21085, MRF5S21090 and MRF5P21180 LDMOSs, to confirm the suitability for Doherty operation. Since the MRF21085 transistor is not suitable, we have excluded it. Two 2.14GHz high power Doherty amplifiers are implemented using two MRF5S21090 and a MRF5P21180, respectively, and are optimized at 40W for high efficiency and good linearity using IS95A 8FA CDMA signal. The performances of the Doherty amplifiers are compared with a conventional balanced class AB amplifier using two MRF5S21090. At 40W average output power, the MRF5S21090 and MRF5P21180 Doherty amplifiers deliver the efficiencies of 34.8% and 40.0%, which represent 11.2% and 16.4% enhancements, respectively, compared to the conventional amplifier. The linearities of all the amplifiers are adjusted to about -31dBc.

A Wideband Envelope Tracking Doherty Amplifier for WiMAX Systems

We have demonstrated a wideband envelope tracking Doherty amplifier. The amplifier is implemented using Eudyna 10-W GaN high electron mobility transistor. For world interoperability for microwave access (WiMAX) signals of the 802.16d and 802.16e, the Doherty amplifier covers the 90 MHz bandwidth (2.3-2.39 GHz) of the Koreas mobile WiMAX (WiBro). The performance of gain, power-added efficiency (PAE), and relative constellation error (RCE) are nearly uniform for the bandwidth. In order to improve the linearity, we have applied the envelope tracking technique to the gate of the Doherty amplifier. The envelope tracking amplifier delivers a significantly improved RCE performance of 35.3dB, which is an enhancement of about 4.3dB, maintaining the high PAE of about 30% for the 802.16 d signal at an average output power of 35 dBm.