Ildu Kim

Optimum operation of asymmetrical-cells-based linear Doherty power Amplifiers-uneven power drive and power matching

We developed a Doherty amplifier with uneven input drive and optimized individual matching for the carrier and peaking cells. In the proposed amplifier, higher input power is delivered to the peaking cell rather than the carrier cell for optimized linear power operation, especially for appropriate load modulation. Both cells are matched differently to further optimize the performance. We analyzed the efficiency of the proposed amplifier as a function of the input drive ratio for the two cells. To interpret the linearity related to the load modulation and harmonic cancellation mechanisms, we simulated the third-order intermodulation amplitude and phase of each cell of the proposed amplifier. For verification, we implemented the asymmetric power amplifier with uneven drive and optimized power matching using Motorolas MRF281SR1 LDMOSFET with a 4-W peak envelope power. For a 2.14-GHz forward-link wireless code-division multiple-access signal, the measured drain efficiency of the amplifier is 40%, and the measured average output power is 33 dBm at an adjacent channel leakage ratio (ACLR) of -35 dBc, while those of the comparable class-AB amplifier are 21% and 30.6 dBm at the same ACLR level, respectively.

The Doherty power amplifier

In this article, we show that the Doherty amplifier is capable of delivering the stringent requirements of the base station power amplifiers. We explain the operation principles, including both linearity and efficiency improvements, and the basic circuit configuration of the amplifier. Advanced design methods to operate across wide bandwidth and improve the linearity are also described. For verification, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal. These results show that the Doherty amplifier is a promising candidate for base station power amplifiers with wide bandwidth, high efficiency, and linearity

Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

Analysis of a Fully Matched Saturated Doherty Amplifier With Excellent Efficiency

A saturated Doherty amplifier based on class-F amplifiers is analyzed in terms of its load modulation behavior, efficiency, and linearity. Simulations included the amplitude ratio and phase difference between the fundamental and third harmonic voltages, the current/voltage waveforms, load lines, and the third-order intermodulation amplitudes/phases of the carrier and peaking amplifiers. The saturated doherty power amplifier was implemented using two Eudyna EGN010MK GaN HEMTs with a 10-W peak envelope power. For a 2.14-GHz forward-fink wideband code-division multiple-access signal, the doherty amplifier delivers an excellent efficiency of 52.4% with an acceptable linearity of -28.3 dBc at an average output power of 36 dBm. Moreover, the amplifier can provide the high linearity performance of -50 dBc using the digital feedback predistortion technique.

High-Efficiency Hybrid EER Transmitter Using Optimized Power Amplifier

This paper describes a new design approach for a power amplifier (PA) of the highly efficient hybrid envelope elimination and restoration (H-EER) transmitter. Since the PA operates mostly at the average power region of the modulation signal, power-added efficiency (PAE) of the PA at the average drain voltage is very important for the overall transmitter PAE. Accordingly, the PA is designed to have a maximum PAE in that region. The performances of the proposed PA and a conventional PA under H-EER operation are evaluated via ADS and MatLab simulations using a behavioral large-signal model of a silicon LDMOSFET, which verifies that the proposed PA has significant advantages for the H-EER transmitter in both PAE and output power. A saturated amplifier, inverse class F, has been implemented using a 5-W peak envelope power LDMOSFET for 3GPP forward-link single-carrier wideband code-division multiple-access at 1 GHz with a peak-to-average power ratio of 9.8 dB. An envelope amplifier is built that has an efficiency of above 68% and peak output voltage of 31 V for an interlock experiment. The overall PAE of the transmitter with a conventional PA is 35.5% at an output power of 29.2 dBm. On the other hand, the transmitter with the proposed PA delivers significantly improved performances: PAE increased by 4% and output power by 2.5 dB. The H-EER transmitter has been linearized by the digital feedback predistortion technique. The measured error vector magnitude is reduced to 1.47% from 6.4%. These results clearly show that the proposed architecture is a good candidate for efficient linear transmitters.

Optimized Design of a Highly Efficient Three-Stage Doherty PA Using Gate Adaptation

We demonstrate an optimized design of a highly efficient three-stage Doherty power amplifier (PA) for the 802.16e mobile world interoperability for microwave access (WiMAX) application at 2.655 GHz. The “three-stage” Doherty PA is the most efficient architecture among the various Doherty PAs for achieving a high peak to average power ratio (PAPR) signal. However, it has a problem in that the carrier PA has to maintain a saturated state with constant output power when the other peaking PAs are turned on. We solved the problem using a gate envelope tracking (ET) technique. For the proper load modulation, the gate biases of the peaking PAs were adaptively controlled, and the peak power and maximum efficiency characteristics along the backed-off output power region were successfully achieved. Using Agilents Advanced Design System and Matlab simulations, the overall behavior of the three-stage Doherty PA with the ET technique employed was fully analyzed, and the optimum design procedure is suggested. For the WiMAX signal with a 7.8-dB PAPR, the measured drain efficiency of the proposed three-stage Doherty PA is 55.4% at an average output power of 42.54 dBm, which is an 8-dB backed-off output power. Digital predistortion was used to linearize the proposed PA. After linearization, a -33.15 dB relative constellation error performance was achieved, satisfying the system specifications. This is the best performance of any 2.655-GHz WiMAX application ever reported, and it clearly shows that the proposed three-stage Doherty PA is suitable as a highly efficient and linear transmitter.

Advanced Doherty Architecture

For modulated signals with a high peak-to-average power ratio (PAPR), the transmitter has to be operated with its average output power backed off for an acceptable linearity at the expense of low efficiency. To achieve high efficiency and high linearity at the same time, both an efficiency enhancement technique and a linearization technique should be utilized. A powerful and reliable linearization technique, digital predistortion (DPD), is currently the most favored method for the linearization of base-station amplifiers [1]-[3]. Possible efficiency enhancement techniques are the hybrid envelope elimination and restoration/envelope tracking technique (H-EER/ET) and the Do-herty technique.

A Wideband Envelope Tracking Doherty Amplifier for WiMAX Systems

We have demonstrated a wideband envelope tracking Doherty amplifier. The amplifier is implemented using Eudyna 10-W GaN high electron mobility transistor. For world interoperability for microwave access (WiMAX) signals of the 802.16d and 802.16e, the Doherty amplifier covers the 90 MHz bandwidth (2.3-2.39 GHz) of the Koreas mobile WiMAX (WiBro). The performance of gain, power-added efficiency (PAE), and relative constellation error (RCE) are nearly uniform for the bandwidth. In order to improve the linearity, we have applied the envelope tracking technique to the gate of the Doherty amplifier. The envelope tracking amplifier delivers a significantly improved RCE performance of 35.3dB, which is an enhancement of about 4.3dB, maintaining the high PAE of about 30% for the 802.16 d signal at an average output power of 35 dBm.

Weighted Polynomial Digital Predistortion for Low Memory Effect Doherty Power Amplifier

We have proposed a simple and effective weighted polynomial digital predistortion algorithm, which consists of weighting, least square polynomial fit, and de-weighting. The weighting factor is introduced to describe the signal distribution statistics and high harmonic generation at a high power region to improve accuracy of the error function. A low memory linear Doherty power amplifier (PA) has been realized with two 90-W peak envelope power LDMOSFETs using memory effect reduction techniques, and the proposed algorithm has been applied to the PA. For the forward-link wideband code division multiple access 3FA signal, the adjacent channel leakage ratio performance at 5-MHz offset is -56 dBc with power-added efficiency of 20.78% at an average power of 40 dBm. The proposed weighting polynomial algorithm provides a significantly reduced error power and superior convergence behavior with improved linearization capability than the conventional polynomial. Moreover, the low memory Doherty amplifier could be linearized for a wideband signal using the simple algorithm without any memory effect compensation

Highly linear three-way Doherty amplifier with uneven power drive for repeater system

We have demonstrated a high linear three-way Doherty amplifier by applying uneven power drive and optimizing the peaking biases and load impedances. The amplifier has been implemented at 2.14GHz using 190-W peak envelope power laterally diffused metal-oxide-semiconductor field-effect transistors. For comparison, a class AB biased amplifier is tested as its counterpart. The two-tone signal and forward-link wideband code-division multiple access (WCDMA) signal have been selected as test signals. At 42dBm (12.5-dB backed-off output power), there are large improvements in the third- and fifth-order intermodulation distortions. For the forward-link four-carrier WCDMA signal, the adjacent channel leakage ratio (ACLR) performances at 5-MHz and 10-MHz offsets are -52.5dBc and -53.4dBc, respectively, and satisfy the generally medium high power amplifier linearity target without using any other linearization circuits. In comparison with the class AB amplifier, the three-way Doherty amplifier with uneven power drive has 9.8-dB lower ACLR at 5-MHz offset while maintaining a comparable drain efficiency of 10.2%.