Young Yun Woo

Analysis and experiments for high-efficiency class-F and inverse class-F power amplifiers

This paper presents analytic and experimental comparisons for high-efficiency class-F and inverse class-F amplifiers. The analytic formula of the efficiencies, output powers, dc power dissipations, and fundamental load impedances of both amplifiers are derived from the ideal current and voltage waveforms. Based on the formula, the performances are compared with a reasonable condition: fundamental output power levels of class-F and inverse class-F amplifiers are conditioned to be identical. The results show that the inverse class-F amplifier has better efficiency than that of class-F amplifiers as the on-resistance of the transistor increases. For experimental comparison, we have designed and implemented the class-F and inverse class-F amplifiers at I-GHz band using a GaAs MESFET and analyzed the measured performances. Experimental results shows 10% higher power-added efficiency of the inverse class-F amplifier than that of the class-F amplifier, which verifies the waveform analysis.

Analysis of a Fully Matched Saturated Doherty Amplifier With Excellent Efficiency

A saturated Doherty amplifier based on class-F amplifiers is analyzed in terms of its load modulation behavior, efficiency, and linearity. Simulations included the amplitude ratio and phase difference between the fundamental and third harmonic voltages, the current/voltage waveforms, load lines, and the third-order intermodulation amplitudes/phases of the carrier and peaking amplifiers. The saturated doherty power amplifier was implemented using two Eudyna EGN010MK GaN HEMTs with a 10-W peak envelope power. For a 2.14-GHz forward-fink wideband code-division multiple-access signal, the doherty amplifier delivers an excellent efficiency of 52.4% with an acceptable linearity of -28.3 dBc at an average output power of 36 dBm. Moreover, the amplifier can provide the high linearity performance of -50 dBc using the digital feedback predistortion technique.

High-Efficiency Hybrid EER Transmitter Using Optimized Power Amplifier

This paper describes a new design approach for a power amplifier (PA) of the highly efficient hybrid envelope elimination and restoration (H-EER) transmitter. Since the PA operates mostly at the average power region of the modulation signal, power-added efficiency (PAE) of the PA at the average drain voltage is very important for the overall transmitter PAE. Accordingly, the PA is designed to have a maximum PAE in that region. The performances of the proposed PA and a conventional PA under H-EER operation are evaluated via ADS and MatLab simulations using a behavioral large-signal model of a silicon LDMOSFET, which verifies that the proposed PA has significant advantages for the H-EER transmitter in both PAE and output power. A saturated amplifier, inverse class F, has been implemented using a 5-W peak envelope power LDMOSFET for 3GPP forward-link single-carrier wideband code-division multiple-access at 1 GHz with a peak-to-average power ratio of 9.8 dB. An envelope amplifier is built that has an efficiency of above 68% and peak output voltage of 31 V for an interlock experiment. The overall PAE of the transmitter with a conventional PA is 35.5% at an output power of 29.2 dBm. On the other hand, the transmitter with the proposed PA delivers significantly improved performances: PAE increased by 4% and output power by 2.5 dB. The H-EER transmitter has been linearized by the digital feedback predistortion technique. The measured error vector magnitude is reduced to 1.47% from 6.4%. These results clearly show that the proposed architecture is a good candidate for efficient linear transmitters.

A New Wideband Adaptive Digital Predistortion Technique Employing Feedback Linearization

We develop a new wideband digital feedback predistortion (WDFBPD) technique for modulated signals with wide bandwidths by combining digital feedback predistortion (DFBPD) linearization and memory-effect compensation techniques. For the experiments, a class-AB amplifier using an LDMOSFET with 90-W peak envelope power is employed. The proposed technique is compared with existing DFBPD and memory polynomial (MP) techniques for a 2.14-GHz forward-link WCDMA 2FA signal with 10-MHz carrier spacing. The experimental results show that the new WDFBPD technique has better linearization performance than conventional DFBPD and lower computational complexity than the MP technique.

Experimental investigation on efficiency and linearity of microwave Doherty amplifier

We have investigated the microwave Doherty amplifier, testing for efficiency and linearity. For the experiment, a 1.4 GHz Doherty amplifier has been implemented using a silicon LDMOSFET. The Doherty amplifier-I (a combination of a class B carrier amplifier and a class C peaking amplifier) and the Doherty amplifier-II (a combination of a class AB carrier amplifier and a class C peaking amplifier) have been compared with class B and AB amplifiers, respectively, using single-tone, two-tone, and forward-link CDMA signals. It demonstrated the superior performance of Doherty amplifiers. The results provide a topology selection guide of the CDMA base station power amplifier to achieve both linearity and efficiency enhancements.

A new empirical large-signal model of Si LDMOSFETs for high-power amplifier design

We propose a new empirical large-signal model of silicon laterally diffused MOSFETs for the design of various modes of high-power amplifiers. The new channel current model has only nine parameters that represent the unique operation principles of a MOSFET. In the channel current model, we include the thermal phenomena of high-power devices. To accurately characterize high-power devices, we incorporate the channel heating and heat-sink heating effects by providing two thermal capacitances and two thermal resistances. Nonlinear capacitances, including deep subthreshold and triode regions, as well as normal saturation regions, are extracted and modeled. For validation of our model, a 1.4-GHz 5-W amplifier is implemented, and the measured and simulated results match very well.

SDR transmitter based on LINC amplifier with bias control

This paper describes a LINC (Linear Amplification using Nonlinear Components) handset transmitter adopting DC bias control. The power amplifier is operated at a saturated output power level and its level is adjusted by DC bias control. Thus the transmitter guarantees high efficiency at all usable output power level. Due to the LINC linearization, it can operate as a linear power amplifier. The new LINC transmitter can be used as a transmitter for software defined radio (SDR), since it can efficiently amplify both the GSM type constant envelope signal and CDMA type non-constant envelope signal, and its control part is very simple and mostly embodied in the digital domain. For verification, a 1.71 GHz LINC prototype transmitter has been implemented and tested. The results, compared with conventional cases, clearly show the suitability of the new LINC transmitter for SDR application.

New predistortion linearizer using low-frequency even-order intermodulation components

We present two types of new predistortion linearizers using low-frequency even-order components. One adopts an in-phase and quadrature balanced modulator as a generator of the third-order intermodulation (IM3) and fifth-order intermodulation (IM5) components and the other adopts a double-balanced diode mixer. Both types are very compact and could independently control the amplitudes and phases of the intermodulation (IM) components. We have analyzed the delay mismatch effect of these predistortion circuits. The result shows that the IM5 components are twice as sensitive than the third ones. Two types of predistorters are implemented and tested at the International Mobile Telecommunications-2000 band. Two tone test results show that the IM3 cancellation is about 23-25 dB and the IM5 is cancelled by about 12-20 dB for both cases. The adjacent channel power ratio is improved by over 11 dB at the broad-band CDMA signal with a chip rate of 4.096 Mc/s, and this improvement is maintained through a broad range of output power level.

Highly linear three-way Doherty amplifier with uneven power drive for repeater system

We have demonstrated a high linear three-way Doherty amplifier by applying uneven power drive and optimizing the peaking biases and load impedances. The amplifier has been implemented at 2.14GHz using 190-W peak envelope power laterally diffused metal-oxide-semiconductor field-effect transistors. For comparison, a class AB biased amplifier is tested as its counterpart. The two-tone signal and forward-link wideband code-division multiple access (WCDMA) signal have been selected as test signals. At 42dBm (12.5-dB backed-off output power), there are large improvements in the third- and fifth-order intermodulation distortions. For the forward-link four-carrier WCDMA signal, the adjacent channel leakage ratio (ACLR) performances at 5-MHz and 10-MHz offsets are -52.5dBc and -53.4dBc, respectively, and satisfy the generally medium high power amplifier linearity target without using any other linearization circuits. In comparison with the class AB amplifier, the three-way Doherty amplifier with uneven power drive has 9.8-dB lower ACLR at 5-MHz offset while maintaining a comparable drain efficiency of 10.2%.

Feedforward amplifier for WCDMA base stations with a new adaptive control method

This paper describes a feedforward amplifier with a new adaptive control method. For the modulated signal with a high peak-to-average ratio, the residual output error level of the feedforward amplifier can be further reduced by adjusting the 1st loop control parameters to have an imperfect signal cancellation since an error amplifier generates less distortion in the case. For verification, a baseband signal simulation and experiments have been performed. A 30 W feedforward amplifier for WCDMA base stations at 2.14 GHz shows a 4 dB improvement of linearization when it is controlled by the proposed method.