Byeong Yong Kong
KAIST
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Publication
Featured researches published by Byeong Yong Kong.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2012
Byeong Yong Kong; In-Cheol Park
An efficient filter synthesis algorithm is proposed to minimize the number of adders required in the design of finite-impulse response filters. Given a specification, a filter can be synthesized by conducting two main steps: coefficient generation and multiplier-block synthesis. While most of previous works have focused on only one of the steps, the proposed algorithm integrates the two steps in an interleaved manner so as to take into account the effect of multiplier-block synthesis in generating coefficients. In addition, the concept of sensitivity is developed to reduce the complexity of computing the variable ranges of coefficients. Experimental results show that the proposed algorithm outperforms previous algorithms in terms of adder cost and takes a relatively short computation time.
IEEE Transactions on Circuits and Systems Ii-express Briefs | 2016
Byeong Yong Kong; Hoyoung Yoo; In-Cheol Park
This brief presents an efficient sorting architecture for successive-cancellation-list decoding of polar codes. In order to avoid performing redundant sorting operations on the metrics that are already sorted in the previous step of decoding, the proposed architecture separately processes the sorted metrics and unsorted ones. In addition, the odd-even sort network is adopted as a basic building block to further reduce the hardware complexity while sustaining low latencies for various list sizes. On average, the proposed architecture requires less than 50% of the compare-and-swap units demanded by the area-efficient sorting networks in the literature.
IEEE Transactions on Very Large Scale Integration Systems | 2014
Byeong Yong Kong; Jihyuck Jo; H. J. Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park
A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. For a (40, 33) code, the proposed architecture reduces the latency and the hardware complexity by ~32% and 9%, respectively, compared with the most recent implementation.
personal, indoor and mobile radio communications | 2016
Byeong Yong Kong; In-Cheol Park
In this paper, we propose a low-complexity symbol detection algorithm for massive multiple-input multiple-output (MIMO) uplink. Grounded on the fact that a primary property of the massive MIMO systems guarantees the convergence of the Jacobi method, the method is exploited in the linear detection so that the estimate of transmitted symbols can be obtained without employing the computationally intensive matrix inversion. In addition, we propose a multiplication-free initial estimate for the Jacobi method in order to lessen the computational complexity further. Owing to the elimination of matrix inversion and the efficient initial estimate, the proposed algorithm achieves near-optimal error-rate performance with fewer computations than the state-of-the-art schemes.
international conference on acoustics, speech, and signal processing | 2015
Byeong Yong Kong; In-Cheol Park
An efficient procedure for frequency estimation is proposed in this paper to alleviate the computational complexity. Grounded on the fact that the frequency of a target signal usually lies in a known range in practical applications, two fundamental steps in the frequency estimation, i.e., the discrete Fourier transform (DFT) and the interpolation of the DFT samples, are modified accordingly. Unlike the previous works focusing on either the DFT or the interpolation, this paper does not decouple the two steps but optimizes the whole procedure comprehensively by considering the interrelationship between the two steps. As a result, the number of operations required for the estimation is remarkably diminished while the performance remains competitive with the recent works.
vehicular technology conference | 2013
Byeong Yong Kong; In-Cheol Park
A simple yet effective scheme is proposed to improve the detection capability of multiple-input multiple-output (MIMO) symbol detectors in wireless communication systems at low signal-to-noise ratio (SNR). The proposed scheme is to change the metric calculation adaptively to the channel SNR, grounded on the fundamental relationship between the detection capability and the bit-error rate (BER) performance with respect to the channel SNR. An efficient hardware architecture implementing the proposed scheme is also presented to show its applicability in a practical sense and it is proven that the architecture induces only a negligible hardware overhead compared to the state-of-the-art MIMO symbol detector. Experimental results show that the proposed scheme can indeed increase the detection capability effectively without degrading the BER performance noticeably.
IEEE Communications Letters | 2013
Byeong Yong Kong; In-Cheol Park
An efficient tree-traversal strategy is proposed in this letter to reduce the computational complexity of soft-output multiple-input multiple-output (MIMO) symbol detection. To minimize unnecessary computations, the proposed algorithm visits a node at most once. Meanwhile, it repetitively reorganizes the set of nodes which are likely to be the maximum-likelihood solution or counter-hypotheses that need to be identified in the detection. As the reorganization directs the algorithm to search only meaningful nodes for the required symbols, the complexity can be effectively mitigated while preserving the max-log optimality. Experimental results claim that the proposed algorithm reduces the number of visited nodes by 36% over the single tree search for a MIMO system equipped with 4 × 4 64-QAM.
IEEE Transactions on Circuits and Systems Ii-express Briefs | 2017
Byeong Yong Kong; In-Cheol Park
Electronics Letters | 2013
Byeong Yong Kong; In-Cheol Park
Electronics Letters | 2016
Byeong Yong Kong; In-Yong Park