Jinook Song

Spur-Free MASH Delta-Sigma Modulation

For multistage noise-shaping (MASH) delta-sigma modulation, this paper presents a new structure that is free of spurs for all input values. The proposed MASH structure cascades several first-order delta-sigma modulators (DSMs) like the traditional MASH structure but has an additional feedforward connection between two adjacent stages. The proposed MASH structure can increase the sequence length and thus reduce spurs. The reason why the proposed MASH structure has a long sequence length for the full input range is mathematically proved, and simulations are performed to verify the effect of the long sequence length. Simulation results show that the performance of the proposed MASH structure is close to that of the ideal DSM. In addition, the proposed MASH structure requires almost the same hardware cost as the traditional MASH structure.

Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines

A new discrete wavelet transform (DWT) architecture is proposed to realize a memory-efficient 2-D DWT processor. The proposed DWT processor conforms to dual-line scanning to remove the transpose buffer. In the previous single-line DWT architectures, the transpose buffer size is proportional to the row size of the image. The conventional dual-line DWT architecture is constructed by using the convolution-based filter structure and replicates registers to alternatively deal with two lines, resulting in a long delay, as well as a number of operators and registers. The proposed architecture is based on the lifting-based DWT to embed the additional registers in the middle of the DWT operation. In addition, the computation topology is optimized for the proposed dual-line DWT architecture to achieve almost the same hardware cost and critical path as the single-line DWT architecture.

Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform

This paper presents a new architecture of 2D discrete wavelet transform (DWT) proposed for JPEG 2000. In the proposed architecture, the image is segmented into tiles each of which is sequentially processed to minimize the size of buffers required to process 2D DWT, and multi-level DWTs are interleaved to reduce the size of the repeat buffer drastically. Compared to the conventional architecture, the overall memory size is reduced by 85% and 92% for 256 times 256 and 512 times 512 images, respectively. The proposed DWT processor needs only 5kB memory for 256 times 256 images, and operates at 250MHz in 0.25-mu technology.

Novel pipelined DWT architecture for dual-line scan

A new discrete wavelet transform (DWT) architecture is proposed in this paper to realize a memory-efficient 2D DWT unit. The proposed DWT architecture alternately processes two lines to remove the transpose buffer whose size is proportional to the image row size. As a result, the hardware complexity of 2D DWT is significantly reduced. To maintain the same critical path delay as that of the previous pipelined DWT, serially concatenated additions are optimized by changing computation topology and applying arithmetic optimization.

Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture

This brief presents a new multistage noise-shaping (MASH) structure that has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed and the noise-shaping capability of the MASH architecture is preserved.

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs

This paper presents an efficient modeling method for the effects of capacitor mismatches in SAR ADCs. As the capacitor mismatch can severely degrade accuracy, it is necessary to determine the limitation of the resolution. We statistically analyze the resolution of the SAR ADCs considering both the traditional approach and the proposed advanced analysis, and the concrete relations between the capacitor mismatch ratio and the maximum achievable resolution are carefully derived. In contrast to the numerical approaches performed in the previous literatures, this analysis results in a simple closed-form expression for the relations. Since the unit-capacitor size can be optimally determined according to the proposed relations, the area and energy consumption of the capacitive DAC in SAR ADCs can be minimized. Massive Monte-Carlo simulations are conducted to verify the proposed relations, and the simulation results support the proposed analysis.

Division-less high-radix interleaved modular multiplication using a scaled modulus

This paper presents a new modular multiplication algorithm developed to remove division-based denormalization. In modular multiplication algorithms, the modular reduction estimates an intermediate quotient by referring to the most significant bits of the intermediate remainder since the modulus is scaled up, however, the modular multiplication results in an enlarged value that should be denormalized at the end. The denormalization has been realized by employing a division operation, which is not an efficient way in the view point of hardware implementation and processing cycles. The proposed modular multiplication is based on the scaled-modular multiplication which replaces the division-based denormalization with the Montgomery modular reduction. As a result, the hardware complexity is reduced compared to the up-to-date modular multiplication architecture.

Implementation of efficient architecture of two-dimensional discrete wavelet transform

This paper presents a new architecture of 2-dimensional discrete wavelet transform for JPEG2000, and the architecture is verified by implementing on FPGA board. The tile-based processing is proposed which removes the transpose buffer effectively.