Byongtae Chung

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.

A single-loop DLL using an OR-AND duty-cycle correction technique

In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage.

A fast GDDR5 read CRC calculation circuit with read DBI operation

The GDDR5 provides cyclic redundancy check (CRC) function to ensure a high speed operation. The GDDR5 calculates the CRC with read data and transmits the results on error detection code (EDC) pins. This paper presents a scheme to reduce calculation time of CRC when the read data bus inversion (DBI) is enabled. This scheme is applied to GDDR5 product manufactured in 66 nm CMOS process technology and its bandwidth is measured to be greater than 4.0 Gbps on the electric field test.

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type [5] with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise-management technique of VPP control and by using a pseudo-rank architecture to suppress VDD noise due to low VPP pumping efficiency.

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation

In this paper, a sense amplifier circuit, which aims to operate with 1V or less supply voltage, is presented. While a conventional sense amplifier uses inverters connected in a cross-coupled manner without any special timing phase, the proposed sense amplifier circuit employs a calibration phase to provide offset voltage margin relaxation. The relaxed amount can be utilized for lowering Vcore, the DRAM core voltage, or increasing the number of Wordlines per Bitline. Also, it can be used for ensuring correct data operations in DRAM fabricated with severer process variation.

A low power and high performance robust digital delay locked loop against noisy environments

A new low power and high performance robust digital delay locked loop is presented. The DLL has dual loops with single replica block, different-type dual DCC at input and output, replay mode function, rising edge scanner and self-calibrated power down controller (SCPDC) for stable power management. The digital DLL used for multi-Gbps graphics SDRAM is fabricated using a 66 nm DRAM process technology. Experimental results show duty-corrected clock from external duty error of plusmn10%, less than 400 cycle locking time, 1.4 GHz operation frequency at 1.7 V and 1.7 GHz at 2.0 V.

Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network

In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitors W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.

Impact of partial EBG PDN on PI, SI and lumped model-based correlation

In this paper, design, modeling and impact of a partial electromagnetic band-gap (EBG) power distribution network (PDN) using remnants of the signal layer in a multilayer printed circuit board (PCB) are presented. A partial EBG PDN is embodied in a conventional four-layer stack-up PCB without any additional layer, and the impact of the proposed method on signal transmission quality improvement and power plane noise mitigation is investigated experimentally. And a lumped model-based simulation method is proposed and correlated with measurement results in both time and frequency domains. It is shown that the proposed method provides an improved signal return current path, resulting in better signal transmission quality and higher signal noise margin than conventional methods. In addition, the method enables lower power noise generation and better noise isolation.