Jin-Hong Ahn

Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications

Self refresh current in modern DRAMs is becoming more difficult problem to handle because the decreasing cell transistor size has a negative effect on the uniformity of capacitor charge. In order to solve this issue, adaptive self refresh(ASR) scheme has been developed. A dual period based refresh is performed in the ASR scheme to reduce power dissipation using row register information. The row register information is adaptively modified according to the cell data retention characteristics. When DRAM enters self refresh mode, only the rows which were activated for write are tested using internal refresh test circuits. The test results are used to choose the appropriate period for the dual period base self refresh operation. This paper demonstrates 512M mobile SDRAM utilizing this adaptive self refresh(ASR) capability to minimize standby power to 150 uA @85degC while maintaining chip area of the conventional scheme using the same process technology.

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

A new low power high performance register-controlled digital delay locked loop (LPRCDLL) is presented. The circuit has fine delay compensation ability, fast delay compensation according to external voltage variation, and inherent duty correction. The digital DLL used for 2Gbps 8M times 32 GDDR3 SDRAM is fabricated using a 0.10mum technology. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1GHz operation frequency at 1.5V, 38mW at 1.5V/1GHz, and a wide locking range from 250MHz to 1GHz

A low power and highly reliable 400Mbps mobile DDR SDRAM with on-chip distributed ECC

512 Mb Mobile SDRAM with on-chip error-correction code (ECC), which supports either single or double data rate and operates on a 1.8 V power supply, is developed. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty. The ratio of ECC area increase compared with the conventional mobile DRAM is 15%, and the fast comparing circuits of built-in Hamming code technique check 12 cell data simultaneously and satisfy the specification of 400Mbps DDR SDRAM. The self refresh period at standby state shows about 6 times increase reducing the self refresh current to be less than 100uA at 85degC. The newly adopted DCCS in the ECC, which is resistant from the clustered failures, and the concurrent row redundancy produce a synergistic fault-tolerance effect. The reliability could be 106 times higher by the ECC than that of the conventional DRAM.

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.

A single-loop DLL using an OR-AND duty-cycle correction technique

In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.

Modulation of molecular hybridization and charge screening in a carbon nanotube network channel using the electrical pulse method

In this paper, we investigate the effect of electrical pulse bias on DNA hybridization events in a biosensor platform, using a Carbon Nanotube Network (CNN) and Gold Nano Particles (GNP) as an electrical channel. The scheme provides both hybridization rate enhancement of bio molecules, and electrical measurement in a transient state to avoid the charge screening effect, thereby significantly improving the sensitivity. As an example, the probe DNA molecules oscillate with pulse trains, resulting in the enhancement of DNA hybridization efficiency, and accordingly of the sensor performances in Tris-EDTA (TE) buffer solution, by as much as over three times, compared to the non-biasing conditions. More importantly, a wide dynamic range of 10(6) (target-DNA concentration from 5 pM to 5 μM) is achieved in human serum. In addition, the pulse biasing method enables one to obtain the conductance change, before the ions within the Electrical Double Layer (EDL) are redistributed, to avoid the charge screening effect, leading to an additional sensitivity enhancement.

3-dimensional local field polarization vector mapping of a focused radially polarized beam using gold nanoparticle functionalized tips.

We have measured local electric field polarization vectors in 3-dimensional space on the nanoscale. A radial polarized light is generated by using a radial polarization converter and focused by an objective lens. Gold nanoparticle functionalized tips are used to scatter the focused field into the far-field region. Two different methods, rotational analyzer ellipsometry and Stokes parameters, are used in determining the polarization state of the scattered light. Two methods give consistent results with each other. Three dimensional local polarization vectors could be reconstructed by applying back transformation of the fully characterized polarizability tensor of the tip.

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type [5] with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise-management technique of VPP control and by using a pseudo-rank architecture to suppress VDD noise due to low VPP pumping efficiency.

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.