Nak-kyu Park

A single-loop DLL using an OR-AND duty-cycle correction technique

In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

As the speed of DRAM increases and the applications spread, DLLs for DRAM require low-jitter characteristics as well as wide operating range in frequency and voltage domains. Even though digital DLLs have improved jitter control schemes [1,2,4], it is difficult to reject the jitter of the external clock in real applications. Whether a PLL or DLL is used, it should have negative delay for phase compensation in DRAM [3]. We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type [5] with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by the power-noise-management technique of VPP control and by using a pseudo-rank architecture to suppress VDD noise due to low VPP pumping efficiency.

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down controller (SPDC) for reducing the standby current during power down, and locking range doubler for wide locking range. The digital DLL used for 3 Gbps 512 Mb GDDR3 SDRAM is fabricated using an 80 nm DRAM Process. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1.5 GHz operation frequency at 1.9 V, and a wide locking range from 50 MHz to 1.5 GHz.

A low power and high performance robust digital delay locked loop against noisy environments

A new low power and high performance robust digital delay locked loop is presented. The DLL has dual loops with single replica block, different-type dual DCC at input and output, replay mode function, rising edge scanner and self-calibrated power down controller (SCPDC) for stable power management. The digital DLL used for multi-Gbps graphics SDRAM is fabricated using a 66 nm DRAM process technology. Experimental results show duty-corrected clock from external duty error of plusmn10%, less than 400 cycle locking time, 1.4 GHz operation frequency at 1.7 V and 1.7 GHz at 2.0 V.