Byoung-Ho Lee

The relationship between inbound open innovation patents and financial performance: evidence from global information technology companies

Most existing studies on the global information technology (IT) sector examine the causal relationship between internally generated patents and corporate performance. However, global IT companies acquire patents not only from internal research and development (R&D), but also from inbound open innovation. Focusing on this, we examine the differential effects of patents from various sources, including (1) internal R&D, (2) university–industry collaboration, and (3) transaction on corporate sales, profits, and market value in 28 global IT companies. We find that patents by internal R&D boost sales, profits, and corporate value. Purchased patents have small, immediate positive effects on market value and profit, but do not increase sales. University–industry collaboration patents drive sales after more than two years, but negatively impact market value. Overall, internal R&D is consistently important for sustainable corporate growth, implying that the acquisition of ideas, technologies, and human resources for internal R&D is the most effective method of inbound open innovation. Purchased patents boost short-term growth, while university–industry collaboration is necessary for mid- and long-term growth. Our study provides the basis for an optimal balance between internal R&D and inbound open innovation, as well as the creation of a financial performance-oriented patent portfolio.

Experimental study of contact edge roughness on sub-100 nm various circular shapes

The measurement of edge roughness has become a hot issue in the semiconductor industry. Especially the contact roughness is being more critical as design rule shrinks. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. However the features currently available in commercial CD-SEM cannot provide a proper solution in monitoring the contact roughness. We had introduced a new parameter R, measurement algorithm and definition of contact edge roughness to quantify CER and CSR in previous paper. The parameter, R could provide an alternative solution to monitor contact or island pattern roughness. In this paper, we investigated to assess optimum number of CD measurement (1-D) and fitting method for CER or CSR. The study was based on a circular contact shape. Some new ideas to quantify CER or CSR were also suggested with preliminary experimental results.

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

AWV: high-throughput cross-array cross-wafer variation mapping

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Study of critical dimension and overlay measurement methodology using SEM image analysis for process control

As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.

Defect distribution study at through silicon via (TSV) bottom by scanning white-light interference microscopy

Distributions of via Depth and bottom CD for TSV wafer have been studied by scanning interference microscopy (Unifire 7900, Nanometrics Inc.). We plotted whole wafer maps for each via depth and bottom CD and found useful relationship between them (i.e. via depth is in inverse proportion to bottom CD in general). Average values of via depth and bottom CD are ~60um and ~4um and their standard deviation values are 1.28% and 5.14% respectively. We also demonstrated kinds of defects at via top (or bottom) which can cause disturbance of total via count during 3D inspection. Our results can be a good introduction to scanning interference tool as a monitoring tool for TSV high volume manufacturing.

Developing an understanding of electron beam imaging of deep contact hole structures using monte carlo and spatial charge distribution simulations

Charging effects on secondary electron (SE) profiles with bias voltage in deep contact holes are investigated. To enhance imaging capability for deep contact holes, the technique of applying a high bias voltage between the objective lens and the sample ground has been developed. However, the physics responsible for the mechanism of extraction of secondary electrons from deep within these structures is not well understood. Following previous work we use Monte Carlo simulations to compute the trajectories of numerous electrons while modeling the charging phenomena to calculate the resultant SE beam profile in a deep contact hole. This software derives the spatial charge distribution within the sample that results from the incident e-beam. The resultant surface potential, arising from areas of positive and negative charge within the sample, creates conditions, which require that the sample be included as an electron-optical element within the system. All of this information is used to calculate the ejected SE trajectories from the deep contact hole structures and to construct quantitative image profiles under specific scanning electron microscope (SEM) operating conditions and contact hole dimensions. The simulated results are compared to experimental results in order to develop a better understanding of e-beam imaging of deep contact hole structures.

Electrical defect SEM review under the various electric circumstances on SAC layer

Traditionally the defects, detected by inspection tools (optic & EBI), have been reviewed through DR-SEM or CD-SEM. Nevertheless, when physical defects are characterized using conventional in-line SEM it is hard to re-detect electrical defects because of the restricted working range in e-beam control. To detect and review electrical defects on contact layer EBI tools were used due to the in-line SEM limitation on electrical defect reviews. However the quality of the image was not acceptable to characterize type of defects due to its low resolution (20~30nm). In this article, the review condition of electrical defect was studied under the various electric conditions on Self Align Contact (SAC) layer. In order to achieve the optimum condition, a wide range of negative and positive conditions were applied using acceleration voltage, I-probe current, cap voltage and scan rate. Under stable weak negative charge conditions, 100% review of electrical and contact bottom defects were achieved. Furthermore, we found the high I-probe current and the appropriate acceleration voltage are main factors which increase the capability to re-detect the electrical defect. In this article, we figure out which defect is electrical defect and non-electrical defect applying to diverse electric conditions on the wafer.

Experimental methodology of contact edge roughness on sub-100-nm pattern

The measurement of edge roughness has become a hot issue in the semiconductor industry. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. However, most of the features are limited by the applicable pattern types. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. The edge roughness is more critical in contact process. However the measurement of contact edge roughness (CER) or contact space roughness (CSR) is more complicated than that of LER or LWR. So far, no formal standard measurement algorithm or definition of contact roughness measurement exists. In this article, currently available features are investigated to assess their representability for CER or CSR. Some new ideas to quantify CER and CSR were also suggested with preliminary experimental results.

Optical characterization of defects on patterned wafers: exploring light polarization

Polarization is an important and useful degree of freedom to explore defect SNR (Signal-to-Noise Ratio) improvement on repetitive memory devices. Sub-wavelength repetitive memory cell structures, especially in process layers of high-refractive-index dielectric and conducting materials, act as polarizer, resulting in a strong dependency of the optical response on polarization direction. In this study, STI layers of two typical memory products, Dynamic and Flash RAM, were selected to investigate defect detection capabilities with different polarization state of illumination light for different layouts. Several defect types, including void and scratch, are investigated. SNR improvement is observed primarily through linear polarization that is parallel to the pattern layout. Flash memory devices exhibit stronger birefringence than DRAM devices.