Chang-lyong Song

Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory

We studied factors which affect cell Vth variation in the floating gate flash memory. By simulation and experiment, we showed that the shape of STI (shallow trench isolation) and the tunnel oxide thickness in the STI edge were the main control factors. For example, sharp and thin oxide in the STI edge caused an uncontrolled F-N gate current in the program or erase operation, which directly indicated the amount of threshold voltage in the flash memory. Furthermore, we found that tunnel oxide thinning was closely related to the activation energy in the oxidation process. Smaller activation energy resulted in better thinning and better cell Vth distribution.

Reduction of plasma-induced damage during intermetal dielectric deposition in high-density plasma

We have attempted to reduce the plasma-induced damage to the thin gate oxides during intermetal dielectric (IMD) gap-fill process by high-density plasma (HDP) chemical vapor deposition (CVD). It was revealed that the optimization of preheating step could reduce the damage. The H/sub 2/-based HDP CVD process was also effective in reducing plasma-induced damage compared with the conventional He-based process. The gate oxide failure was reduced remarkably at the low deposition temperatures less than 400/spl deg/C. Both the significant damage reduction and the excellent gap-fill performance were achieved by the adoption of the phosphorus silicate glass (PSG) using the low temperature H/sub 2/-based HDP CVD technique.

Optical characterization of defects on patterned wafers: exploring light polarization

Polarization is an important and useful degree of freedom to explore defect SNR (Signal-to-Noise Ratio) improvement on repetitive memory devices. Sub-wavelength repetitive memory cell structures, especially in process layers of high-refractive-index dielectric and conducting materials, act as polarizer, resulting in a strong dependency of the optical response on polarization direction. In this study, STI layers of two typical memory products, Dynamic and Flash RAM, were selected to investigate defect detection capabilities with different polarization state of illumination light for different layouts. Several defect types, including void and scratch, are investigated. SNR improvement is observed primarily through linear polarization that is parallel to the pattern layout. Flash memory devices exhibit stronger birefringence than DRAM devices.

Novel method of under-etch defect detection for contact layers based on Si substrate using optic wafer inspection tools

As the design rules of semiconductor devices have decreased, the detection of critical killer defect has became more important. One of killer defect is under-etch defect caused by insufficient contact etch. Although very low throughput only e-beam inspection tool has used for monitoring tools of under-etch defect because optic wafer inspection does not have enough defect signal to detect that on a contact layer. In this study, a new method is suggested for detection of under-etch defect using optic wafer inspection tools which have high throughput and repeatability.

Characterization analysis study of μ-bridge defect using simulation and wafer inspection tools

As the design rules of semiconductor devices continue to decrease, the detection of critical killer defects has become more difficult. In this paper, μ-bridge defects are studied. In order to detect special μ-bridges, both direct inspection and simulation techniques were employed. The inspection technologies used include brightfield, darkfield, and electron-beam inspection (EBI) tools, while the simulation analysis uses charge calculations and Monte Carlo scattering simulation. Special μ-bridge defects were only captured by the EBI tool and verified by focused ion beam (FIB) milling. This result corresponds to simulation data.

Abnormal gate oxide thickening at active edge with SiN-linered shallow trench isolation

Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-lineared shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layers in STI. Other structural parameters, such as the thickness of trench sidewall oxide, liner SiN and sacrificial oxide, are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and shown to be effective in suppressing it. Electrical properties, which are susceptible to the extent of GOTAE, are also presented in this paper.

Is it possible to improve MEEF

As the design rule of device has shrunken, obtaining a feasible process window at low k1 factor in photolithography is the major concerning in order to shorten the total period from development to the mass production of devices. In this low k1 factor region, a tiny CD variation on mask might be increased abruptly on the wafer. In particular, such variation so called MEEF (Mask Error Enhancement Factor) is closely related with various types of process parameter. In this paper, we reviewed optimized process condition to minimize MEEF and defined uDoF (Usable Depth of Focus) considering a correlation between MEEF and DoF (Depth of Focus).

Effect of development process time on the surface of photoresist with various chemical compositions investigated by atomic force microscopy

Understanding the nature of photo-resist (PR) dissolution during the development process is the important factor to accomplish high-precision critical dimension (CD) control in photolithography. In this report, we investigate the effect of each process variable on the PR pattern CD size and surface roughness by scanning electron microscopy (SEM) and atomic force microscopy (AFM). From these experiments, we found out that the major factor to affect the CD and surface roughness control was the puddle time. On the basis of these result, we investigated the relationship between puddle time and chemical compositions of PR. According to the puddle time, top surface of PR became rougher, but finally converged to some value. As the molecular weight and protecting ratio of the PR increased, the degree of surface roughness of the PR increased. Soft bake temperature, which is one of the variables in PR coating process, also affected the surface roughness of the PR. These results must be useful data for the optimization of new developing recipe for the new PR systems which will achieve next generation photolithography.