Soo-bok Chin

Successful application of angular scatterometry to process control in sub-100-nm DRAM device

As DRAM (Dynamic Random Access Memory) device continuously decreases in chip size, an increased speed and more accurate metrology technique is needed to measure CD (critical dimension), film thickness and vertical profile. Scatterometry is an optical metrology technique based on the analysis of scattered (or diffracted) light from periodic line and space grating and uses 2θ angular method (ACCENT Optical Technologies CDS-200). When a light source is irradiated into the periodic pattern, the scattered intensity signal of zero-th order as a function of incident angle is measured. By analyzing these scattered signals, various parameters of the periodic pattern such as CD, vertical profile, mapping of substrate structure, film thickness and sidewall angle can be determined. Advantages of scatterometry are that drastic decreased measuring time and acquirement of CD, vertical profile, film thickness and sidewall angle by just one measurement. In this paper we will discuss various applications of scatterometry to sub-100nm DRAM structures of straight line and space and curved line and space patterns. Details of the correlation with CD-SEM (Scanning Electron Microscope) of standard metrology tool and repeatability of measured CD values will be discussed. As diverse applications, results of in-field, in-wafer and wafer-to-wafer CD monitoring, STI (Shallow Trench Isolation) depth monitoring and matching of vertical profile with V-SEM (Vertical SEM) will be also presented.

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Highly effective and accurate weak point monitoring method for advanced design rule (1x nm) devices

Historically when we used to manufacture semiconductor devices for 45 nm or above design rules, IC manufacturing yield was mainly determined by global random variations and therefore the chip manufacturers / manufacturing team were mainly responsible for yield improvement. With the introduction of sub-45 nm semiconductor technologies, yield started to be dominated by systematic variations, primarily centered on resolution problems, copper/low-k interconnects and CMP. These local systematic variations, which have become decisively greater than global random variations, are design-dependent [1, 2] and therefore designers now share the responsibility of increasing yield with manufacturers / manufacturing teams. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. The semiconductor industry is currently limited to 193 nm scanners and no relief is expected from the equipment side to prevent / eliminate these systematic hotspots. Hence we have seen a lot of design houses coming up with innovative design products to check hotspots based on model based lithography checks to validate design manufacturability, which will also account for complex two-dimensional effects that stem from aggressive scaling of 193 nm lithography. Most of these hotspots (a.k.a., weak points) are especially seen on Back End of the Line (BEOL) process levels like Mx ADI, Mx Etch and Mx CMP. Inspecting some of these BEOL levels can be extremely challenging as there are lots of wafer noises or nuisances that can hinder an inspector’s ability to detect and monitor the defects or weak points of interest. In this work we have attempted to accurately inspect the weak points using a novel broadband plasma optical inspection approach that enhances defect signal from patterns of interest (POI) and precisely suppresses surrounding wafer noises. This new approach is a paradigm shift in wafer inspection by leveraging systematic defect locations for high sensitivity inspection, thereby enhancing the discovery and monitoring of yield-limiting defects at traditional optical inspection throughput.

Defect distribution study at through silicon via (TSV) bottom by scanning white-light interference microscopy

Distributions of via Depth and bottom CD for TSV wafer have been studied by scanning interference microscopy (Unifire 7900, Nanometrics Inc.). We plotted whole wafer maps for each via depth and bottom CD and found useful relationship between them (i.e. via depth is in inverse proportion to bottom CD in general). Average values of via depth and bottom CD are ~60um and ~4um and their standard deviation values are 1.28% and 5.14% respectively. We also demonstrated kinds of defects at via top (or bottom) which can cause disturbance of total via count during 3D inspection. Our results can be a good introduction to scanning interference tool as a monitoring tool for TSV high volume manufacturing.

Electrical defect SEM review under the various electric circumstances on SAC layer

Traditionally the defects, detected by inspection tools (optic & EBI), have been reviewed through DR-SEM or CD-SEM. Nevertheless, when physical defects are characterized using conventional in-line SEM it is hard to re-detect electrical defects because of the restricted working range in e-beam control. To detect and review electrical defects on contact layer EBI tools were used due to the in-line SEM limitation on electrical defect reviews. However the quality of the image was not acceptable to characterize type of defects due to its low resolution (20~30nm). In this article, the review condition of electrical defect was studied under the various electric conditions on Self Align Contact (SAC) layer. In order to achieve the optimum condition, a wide range of negative and positive conditions were applied using acceleration voltage, I-probe current, cap voltage and scan rate. Under stable weak negative charge conditions, 100% review of electrical and contact bottom defects were achieved. Furthermore, we found the high I-probe current and the appropriate acceleration voltage are main factors which increase the capability to re-detect the electrical defect. In this article, we figure out which defect is electrical defect and non-electrical defect applying to diverse electric conditions on the wafer.

Experimental methodology of contact edge roughness on sub-100-nm pattern

The measurement of edge roughness has become a hot issue in the semiconductor industry. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. However, most of the features are limited by the applicable pattern types. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. The edge roughness is more critical in contact process. However the measurement of contact edge roughness (CER) or contact space roughness (CSR) is more complicated than that of LER or LWR. So far, no formal standard measurement algorithm or definition of contact roughness measurement exists. In this article, currently available features are investigated to assess their representability for CER or CSR. Some new ideas to quantify CER and CSR were also suggested with preliminary experimental results.

Optical characterization of defects on patterned wafers: exploring light polarization

Polarization is an important and useful degree of freedom to explore defect SNR (Signal-to-Noise Ratio) improvement on repetitive memory devices. Sub-wavelength repetitive memory cell structures, especially in process layers of high-refractive-index dielectric and conducting materials, act as polarizer, resulting in a strong dependency of the optical response on polarization direction. In this study, STI layers of two typical memory products, Dynamic and Flash RAM, were selected to investigate defect detection capabilities with different polarization state of illumination light for different layouts. Several defect types, including void and scratch, are investigated. SNR improvement is observed primarily through linear polarization that is parallel to the pattern layout. Flash memory devices exhibit stronger birefringence than DRAM devices.

Optical analysis on the wafer defect inspection for yield enhancement

This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

Ellipsometric inspection of the inner surface of pellicle-covered masks

Crystal growth and haze formation on photomasks become serious problems in UV lithography. As the wavelength becomes shorter, photons carry more energy, so the chances of having a photochemical reaction become much higher. Pellicle, adhesive, residue from cleaning or resist strip process, and any contaminant in air can react with UV to form unwanted crystals and a haze layer on reticles. These will reduce the light transmission during exposure process. Thus, frequent mask inspection and periodic mask cleaning are needed to overcome these problems. However, these will in turn increase manufacturing cost and reduce mask life. Thus, a proper mask inspection tool is required to provide early warning of haze formation. In this work, we devised a new ellipsometric technique to investigate the inner surface of mask without removing pellicle. Ellipsometry is known to have mono-layer sensitivity and it can be used to measure any film or partial film formed on non-patterned spot in early stage of growth. However, when a pellicle covers the surface of mask, the ellipsometric data reflected from surface are extremely distorted due to the non-normal transmission through the pellicle. Thus, data analysis becomes extremely difficult without knowing the optical properties of pellicles. In order to solve this problem we developed compensation technique in which two blank pellicles are situated in the optical path in a way to compensate the polarization changes caused by the pellicle on mask. With this method, the conventional ellipsometry spectra of {Δ, Ψ} are deduced.

Novel method of under-etch defect detection for contact layers based on Si substrate using optic wafer inspection tools

As the design rules of semiconductor devices have decreased, the detection of critical killer defect has became more important. One of killer defect is under-etch defect caused by insufficient contact etch. Although very low throughput only e-beam inspection tool has used for monitoring tools of under-etch defect because optic wafer inspection does not have enough defect signal to detect that on a contact layer. In this study, a new method is suggested for detection of under-etch defect using optic wafer inspection tools which have high throughput and repeatability.