Dongchul Ihm

Experimental study of contact edge roughness on sub-100 nm various circular shapes

The measurement of edge roughness has become a hot issue in the semiconductor industry. Especially the contact roughness is being more critical as design rule shrinks. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. However the features currently available in commercial CD-SEM cannot provide a proper solution in monitoring the contact roughness. We had introduced a new parameter R, measurement algorithm and definition of contact edge roughness to quantify CER and CSR in previous paper. The parameter, R could provide an alternative solution to monitor contact or island pattern roughness. In this paper, we investigated to assess optimum number of CD measurement (1-D) and fitting method for CER or CSR. The study was based on a circular contact shape. Some new ideas to quantify CER or CSR were also suggested with preliminary experimental results.

Accelerating litho technology development for advanced design node flash memory FEOL by next-generation wafer inspection and SEM review platforms

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Highly effective and accurate weak point monitoring method for advanced design rule (1x nm) devices

Historically when we used to manufacture semiconductor devices for 45 nm or above design rules, IC manufacturing yield was mainly determined by global random variations and therefore the chip manufacturers / manufacturing team were mainly responsible for yield improvement. With the introduction of sub-45 nm semiconductor technologies, yield started to be dominated by systematic variations, primarily centered on resolution problems, copper/low-k interconnects and CMP. These local systematic variations, which have become decisively greater than global random variations, are design-dependent [1, 2] and therefore designers now share the responsibility of increasing yield with manufacturers / manufacturing teams. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. The semiconductor industry is currently limited to 193 nm scanners and no relief is expected from the equipment side to prevent / eliminate these systematic hotspots. Hence we have seen a lot of design houses coming up with innovative design products to check hotspots based on model based lithography checks to validate design manufacturability, which will also account for complex two-dimensional effects that stem from aggressive scaling of 193 nm lithography. Most of these hotspots (a.k.a., weak points) are especially seen on Back End of the Line (BEOL) process levels like Mx ADI, Mx Etch and Mx CMP. Inspecting some of these BEOL levels can be extremely challenging as there are lots of wafer noises or nuisances that can hinder an inspector’s ability to detect and monitor the defects or weak points of interest. In this work we have attempted to accurately inspect the weak points using a novel broadband plasma optical inspection approach that enhances defect signal from patterns of interest (POI) and precisely suppresses surrounding wafer noises. This new approach is a paradigm shift in wafer inspection by leveraging systematic defect locations for high sensitivity inspection, thereby enhancing the discovery and monitoring of yield-limiting defects at traditional optical inspection throughput.

Defect distribution study at through silicon via (TSV) bottom by scanning white-light interference microscopy

Distributions of via Depth and bottom CD for TSV wafer have been studied by scanning interference microscopy (Unifire 7900, Nanometrics Inc.). We plotted whole wafer maps for each via depth and bottom CD and found useful relationship between them (i.e. via depth is in inverse proportion to bottom CD in general). Average values of via depth and bottom CD are ~60um and ~4um and their standard deviation values are 1.28% and 5.14% respectively. We also demonstrated kinds of defects at via top (or bottom) which can cause disturbance of total via count during 3D inspection. Our results can be a good introduction to scanning interference tool as a monitoring tool for TSV high volume manufacturing.

Experimental methodology of contact edge roughness on sub-100-nm pattern

The measurement of edge roughness has become a hot issue in the semiconductor industry. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. However, most of the features are limited by the applicable pattern types. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. The edge roughness is more critical in contact process. However the measurement of contact edge roughness (CER) or contact space roughness (CSR) is more complicated than that of LER or LWR. So far, no formal standard measurement algorithm or definition of contact roughness measurement exists. In this article, currently available features are investigated to assess their representability for CER or CSR. Some new ideas to quantify CER and CSR were also suggested with preliminary experimental results.

Optimizing inspection recipe by using virtual inspector virtual analyzer and failure bitmap

This paper presents a novel systematic methodology to identify yield limiting killer defects by using KLA-Tencors wafer inspection tools, Klarity Bitmap software and VIVA (Virtual Inspector Virtual Analyzer). This methodology covers two approaches: optimize inspection recipe through short-loop wafers from ADI (After-Develop Inspection) to AEI (After-Etch Inspection); re-optimize inspection recipe by using bitmap failures from Klarity Bitmap as hot spots to VIVA. The results of this study demonstrated that the chipmakers can potentially shorten the learning cycle for identifying killer defects by using this method.

Optical analysis on the wafer defect inspection for yield enhancement

This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

Applications of AFM in semiconductor R&D and manufacturing at 45 nm technology node and beyond

Continuing demand for high performance microelectronic products propelled integrated circuit technology into 45 nm node and beyond. The shrinking device feature geometry created unprecedented challenges for dimension metrology in semiconductor manufacturing and research and development. Automated atomic force microscope (AFM) has been used to meet the challenge and characterize narrower lines, trenches and holes at 45nm technology node and beyond. AFM is indispensable metrology techniques capable of non-destructive full three-dimensional imaging, surface morphology characterization and accurate critical dimension (CD) measurements. While all available dimensional metrology techniques approach their limits, AFM continues to provide reliable information for development and control of processes in memory, logic, photomask, image sensor and data storage manufacturing. In this paper we review up-todate applications of automated AFM in every mentioned above semiconductor industry sector. To demonstrate benefits of AFM at 45 nm node and beyond we compare capability of automated AFM with established in-line and off-line metrologies like critical dimension scanning electron microscopy (CDSEM), optical scatterometry (OCD) and transmission electronic microscopy (TEM).

Compact X‐ray Tool For Critical‐Dimension Metrology

Small Angle X‐ray Scattering (SAXS) is a possible candidate to complement and, in a longer term, to replace existing methods like CD‐SEM and OCD for measurements of CD profiles. Previously reported CD‐SAXS results were very promising; however as obtained using bulky sources as synchrotron, they are most often restricted to research rather than production control. We have designed a pilot set‐up (XCD™) around μ‐focus X‐tube, high‐luminosity focusing mirror‐monochromator and pixilated detector, having in mind that after further optimization of the components, the tool will have a suitable footprint and acceptable throughput. The system operates on MoKα (17.4 keV) beam shining through the wafer, from below. The measurement spot size is 100 μ. The angular resolution allows to measure structures with a pitch 100 nm and below. A software package was developed to simulate and process XCD spectra, taking into account all the components contributing to the instrumental function of the system. A special technique w...