Chorng-Ping Chang

Fabrication of

Segmented-channel Si₁_-_xGe_x/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si₁_-_xGe_x/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si₁_-_xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher <i>I</i>_ON for <i>I</i>_OFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}

Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.

pMOSFETs Using Corrugated Substrates for Improved

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

I_{\rm ON}

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

and Reduced Layout-Width Dependence

This paper describes novel Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows advantages in threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. By demonstrating better VTH variability, superior conductivity and gap fill, Co-Al shows extendibility to the 11nm metal gate and beyond.

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

This paper describes a novel scheme of metal gate integration to achieve precise threshold voltage (VTH) control and multiple VTH, by using metal composition and ion implantation (I/I) into work function metal (WFM). Moreover, WFM full fill is demonstrated with in situ barrier metal to satisfy the conductance requirement of sub-10 nm node gate.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

RF-PVD was investigated as a metal oxide cap deposition process to tune the effective work function in a gate first flow for high-k metal gate stacks. Samples with an aluminum oxide cap layer showed a large flat band voltage shift at minimal equivalent oxide thickness increase by about 0.1 nm. It was confirmed that RF-PVD induced no additional charge damage. Extended RF-PVD process runs also promised a robust process for high-k metal gate device manufacturing.

Wafer edge polishing process for defect reduction during immersion lithography

Pseudomorphic Ge_0.91Sn_0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge_0.91Sn_0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on <;110> channel direction is observed using external transverse uniaxial tensile strain (~0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I_on/I_off ratio, and strain-enhanced mobility are obtained in this work.

Replacement metal gate extendible to 11 nm technology

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO₂ was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N₂O/H₂ was also varied from 5Å to 10Å. The threshold voltage (V_th) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.