Bingxi Wood

Fabrication of

Segmented-channel Si₁_-_xGe_x/Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated Si₁_-_xGe_x/Sisubstrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated Si₁_-_xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher <i>I</i>_ON for <i>I</i>_OFF = 10 nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}

This paper presented the selective epitaxial germanium growth on silicon by trench filling and doping. The process operated in a reaction rate limited regime at a low temperature (350°C to 400°C) to ensure reasonable growth rate, decent surface morphology, and high dopant incorporation in Ge.

pMOSFETs Using Corrugated Substrates for Improved

III-V materials are candidates for high mobility channel and low contact resistance SD at 5nm technology node and beyond [1]. Traditional Si+ ion implant of In0.53Ga0.47As at room temperature causes amorphization of fin and formation of stacking fault defects upon activation anneal. We have demonstrated heated implant can eliminate amorphization induced crystalline damages and improve fin conductance.

I_{\rm ON}

Segmented-channel Si_1-xGe_x/Si pMOSFETs are fabricated using a conventional process, starting with a corrugated Si_1-xGe_x/Si substrate. As compared with control devices fabricated using the same process but starting with a non-corrugated Si_1-xGe_x/Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher I_ON for I_OFF=10 nA per μm layout width) due to enhanced hole mobility, and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region.

and Reduced Layout-Width Dependence

The 10-7 nm CMOS nodes require that ρc be reduced to <; 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

Selective Epitaxial Germanium Growth on Silicon - Trench Fill and In Situ Doping

The quasi-planar segmented-channel MOSFET (SegFET) design provides an evolutionary pathway for continued CMOS technology scaling [1], and can be fabricated using a conventional process flow starting with a corrugated substrate [2]. Fig. 1 shows a schematic plan view and cross-sectional views of the SegFET structure, whose channel region consists of parallel stripes of equal width (Wstripe) isolated by very shallow trench isolation (VSTI) dielectric material which extends below the source/ drain extensions but which can be much shallower than the STI dielectric material used to isolate transistors. The fringing electric fields through the VSTI regions provide for enhanced gate control of the channel potential, so that the SegFET exhibits better short channel behavior compared to the conventional MOSFET [2]. To achieve improved on-state performance, mobility enhancement techniques can be employed; for example, silicon-germanium (Si1-xGex) can be used as the channel material to enhance p-channel MOSFET performance [3-4]. This work investigates the selective epitaxial growth of Si and Si1-xGex layers to form corrugated-Si/Si1-xGex substrates for enhanced p-channel SegFET performance.