Byron Wicks

A 60-GHz fully-integrated Doherty power amplifier based on 0.13-μm CMOS process

A sixty-gigahertz (60-GHz) Doherty power amplifier (PA) has been designed and implemented on 0.13 mum RF-CMOS for use in an integrated 60-GHz transceiver. The fully-integrated design implements the main and auxiliary amplifiers, matching networks, and input and output transmission line networks on-chip. The prototype operating from a 1.6-V supply exhibits an output referred P1dB of 7.0 dB, a PSAT of +7.8 dBm, with peak power gain of 13.5 dB, a 3-dB bandwidth of 6.7 GHz, and 3.0 % PAE. The die area is 1.8 mm2. This amplifier achieves the highest reported figure of merit for power amplifiers of any published millimeter-wave PA on CMOS.

A 60-GHz transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds are smaller in size with lower power consumption and cost than existing technology consequently high speed transceivers operating at 60 GHz and delivering multi-gigabit per second are receiving significant research interest. This paper describes a 60-GHz transmitter developed and tested on a 130-nm CMOS process.

Issues in the Implementation of a 60GHz Transceiver on CMOS

The spectrum around 60 GHz is available for unlicensed operation in many regulatory domains including the USA, Japan, Canada and Australia. One of the applications of this spectrum is for short range communication systems. These systems are designed to deliver gigabit speeds, consuming small amount of power in small form factor. The small factor is achieved because passive components scale with carrier frequency and at 60GHz components such as: transmit receive filters, passives and antennas are candidates for inclusion on the die. Integrating RF, mixed signal and digital components is another important step towards reducing system cost and form factor. In order to achieve low cost and high digital integration CMOS is the process of choice. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages all of which make millimeter wave RF design particularly challenging. In this paper we outline the issues in the implementation of a Gigabit per second 60GHz Transceiver-on-Chip using CMOS.

Implementation of a Gigabit Per Second Millimetre Wave Transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds, are smaller in size, and have lower power consumption and cost. This motivates research to develop transceiver-on-chip and transceiver-in-a-package technologies. Recent advances in millimetre wave electronics have meant that significant portions of the system can now be integrated onto a single substrate or package. In order to achieve low costs and high digital integration CMOS is the process of choice as CMOS is the standard and a cost effective process for building digital circuits. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages. This makes millimetre wave wireless transceiver on a chip design particularly challenging. In this paper we outline the development of a gigabit transceiver-on-chip using CMOS and outline the performance of the fabricated components.

A 60-GHz power amplifier and transmit/receive switch for integrated CMOS wireless transceivers

The design of two critical building blocks for the realization of an all-integrated transceiver, the power amplifier (PA) and the transmit/receive switch (T/R switch), using a 130-nm CMOS process will be presented. The PA operating from a 2.5-V supply exhibits an output referred P1dB of 9.0 dB, a PSAT of+13.1 dBm, with peak power gain of 14.9 dB, a 3-dB bandwidth of 6.7 GHz, and 2.8 % power added efficiency (PAE). The T/R switch has an insertion loss from 3.5 to 4.9 dB, an isolation between transmit and receive ports better than 30 dB, and return losses at active ports less than -11 dB across the 57-66 GHz band. The input referred P1dB of the switch is 7.2 dBm.

A 75 - 95 GHz Wideband CMOS Power Amplifier

In this paper, a 75 - 95 GHz wideband power amplifier (PA) in 0.13-mum CMOS is implemented to explore the feasibility of low-cost CMOS technology for use in 71 - 76 GHz, 81 - 86 GHz and 92 - 95 GHz fixed point-to-point link bands and the 77-GHz vehicular radar band. The fully-integrated design incorporates the power amplifier, matching networks, and input and output transmission line networks on-chip. The designed amplifier achieves small signal gain of 6.0 dB at 77 GHz, a 3-dB bandwidth of 75 - 95 GHz and delivers a saturated output power of 8.1 dBm.

A 60-GHz direct-conversion transmitter in 130-nm CMOS

This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.