Chien M. Ta

A 60-GHz CMOS Transmit/Receive Switch

A single-pole double-throw (SPDT) transmit/receive switch (T/R switch) operating in the 57-66 GHz band is implemented on a 130-nm CMOS process. The switch exhibits an insertion loss from 4.5 dB to 5.8 dB, an isolation from 24.1 dB to 26 dB, a return loss at antenna port from -9.2 dB to -10.5 dB, and a return loss at Tx/Rx port below -15 dB for the frequency band. With a control voltage of 1.2 V the IP1dB of the switch is 4.1 dBm. The switch features fast switching speed with rise-time and fall-time of 400 ps and 360 ps, respectively. This is the first CMOS T/R switch designed for very short range radio in 60-GHz band.

A CMOS 77-GHz Receiver Front-End for Automotive Radar

This paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76-77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a LC resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.

A 60-GHz transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds are smaller in size with lower power consumption and cost than existing technology consequently high speed transceivers operating at 60 GHz and delivering multi-gigabit per second are receiving significant research interest. This paper describes a 60-GHz transmitter developed and tested on a 130-nm CMOS process.

A 77 GHz CMOS low noise amplifier for automotive radar receiver

This paper presents the design of a low noise amplifier (LNA) for automotive radar application operating at 76-77 GHz. The LNA consists of 5 cascade common source amplifiers. The output of each stage is positioned close to the gate of the next stage creating a LC resonance output load, therefore complex interstage matching networks are eliminated. Moreover, transmission lines (T Ls) are utilized to create matching and load inductors. As a result, chip size is significantly reduced. The proposed LNA is implemented in a 65 nm CMOS technology and measurement results show 11 dB voltage gain, and 7.8 dB noise figure (NF) while dissipating 21.5 mA from 1.2 V supply.

Issues in the Implementation of a 60GHz Transceiver on CMOS

The spectrum around 60 GHz is available for unlicensed operation in many regulatory domains including the USA, Japan, Canada and Australia. One of the applications of this spectrum is for short range communication systems. These systems are designed to deliver gigabit speeds, consuming small amount of power in small form factor. The small factor is achieved because passive components scale with carrier frequency and at 60GHz components such as: transmit receive filters, passives and antennas are candidates for inclusion on the die. Integrating RF, mixed signal and digital components is another important step towards reducing system cost and form factor. In order to achieve low cost and high digital integration CMOS is the process of choice. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages all of which make millimeter wave RF design particularly challenging. In this paper we outline the issues in the implementation of a Gigabit per second 60GHz Transceiver-on-Chip using CMOS.

A 60-GHz power amplifier and transmit/receive switch for integrated CMOS wireless transceivers

The design of two critical building blocks for the realization of an all-integrated transceiver, the power amplifier (PA) and the transmit/receive switch (T/R switch), using a 130-nm CMOS process will be presented. The PA operating from a 2.5-V supply exhibits an output referred P1dB of 9.0 dB, a PSAT of+13.1 dBm, with peak power gain of 14.9 dB, a 3-dB bandwidth of 6.7 GHz, and 2.8 % power added efficiency (PAE). The T/R switch has an insertion loss from 3.5 to 4.9 dB, an isolation between transmit and receive ports better than 30 dB, and return losses at active ports less than -11 dB across the 57-66 GHz band. The input referred P1dB of the switch is 7.2 dBm.

A 60-GHz variable delay line on CMOS for steerable antennae in wireless communication systems

A variable delay line (VDL) is designed on a 130-nm CMOS process. Post-layout simulation results show that the VDL has a phase tuning range of 100 degrees at 60 GHz. It exhibits a wideband matching to 50-Ohm terminations from 20 GHz up to exceeding 80 GHz. The group delay variation is less than 4 ps within a bandwidth of 10 GHz. At its maximum phase shift, the VDL introduces a loss of 6 dB. The design features a small footprint of 430 mum times 220 mum and can be easily extended to provide wider phase tuning range.

A 60-GHz direct-conversion transmitter in 130-nm CMOS

This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.

A 7GHz 1mV-input-resolution comparator with 40mV-input-referred-offset compensation capability in 65NM CMOS

A 7GHz-clock 1mV-input-resolution comparator is designed and simulated in a 65nm CMOS process. The comparator offset is compensated by changing the body voltages of the input differential triple-well NFET transistor pair. A reset switch is added between two regeneration nodes to further match voltages in reset phase. Kickback noise in this comparator is reduced by isolating regeneration nodes of the cross-coupled inverters from the input nodes. Simulated delay of the comparator at ΔVin = 1mV@VDD=1.2V is 69ps. The comparator can operate with a 7GHz clock and a differential input voltage as small as 1mV@VDD=1.2V and can compensate for an input-referred offset of up to 40mV.

A current-switching phase shifter for millimeter-wave applications

A method for realizing a phase shifter by employing switching transistors and transmission lines is proposed. The presented current switching phase shifter performs phase shifting by steering a current source to appropriate position on a transmission line. A 60-GHz phase shifter is implemented on a 65-nm CMOS technology using this method. The phase shifter can provide four quadrature phases for input signals in the frequency range from 57 to 66 GHz. The phase shifter introduces a maximum insertion loss of less than 3 dB and a noise figure from 4.3 to 6.1 dB, by post-layout simulation. The IIP3 is 1.2 dBm and the power consumption is 9 mW from a 1.5 V power supply.