Y. Mo

A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed Millimeter-Wave Wireless Systems

Millimeter-wave communication systems are now receiving significant interest. One of the applications of these systems is for short range communication delivering multi-gigabit per second performance. An important component in these high speed communication systems is the frequency synthesis where the internally generated high frequency voltage controlled oscillator (VCO) output is stabilized by comparing it to a low frequency and low phase noise external crystal. In order to compare and stabilize the output, frequency dividers are utilized in the phase locked loop. Current Mode Logic (CML) dividers provide reasonably large division bandwidth, which can match the VCOs wide-range output frequency. The design procedure of the CML frequency divider involves determining transistor sizes that ensure self-oscillation. However, this condition is sufficient but not necessary to design a divider. In this paper a new method to optimize the transistor sizes for CML frequency dividers is proposed which is shown to increase the maximum operating frequency and reduce the power dissipation. The proposed method is used to build a 2:1 static CML divider, fabricated on 0.13-mum CMOS, which achieves a division range from 12 to 40 GHz with power dissipation of 12 mW.

A 60-GHz transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds are smaller in size with lower power consumption and cost than existing technology consequently high speed transceivers operating at 60 GHz and delivering multi-gigabit per second are receiving significant research interest. This paper describes a 60-GHz transmitter developed and tested on a 130-nm CMOS process.

Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequency Divider Based on LC-tank

In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the dividers performance. The proposed CML frequency divider contains four spiral inductors and is fabricated on standard 130-nm CMOS technology. The division range of the proposed divider was measured from 30 GHz to 50 GHz with 11.7 mW power dissipation at a 1.5-V supply voltage.

Issues in the Implementation of a 60GHz Transceiver on CMOS

The spectrum around 60 GHz is available for unlicensed operation in many regulatory domains including the USA, Japan, Canada and Australia. One of the applications of this spectrum is for short range communication systems. These systems are designed to deliver gigabit speeds, consuming small amount of power in small form factor. The small factor is achieved because passive components scale with carrier frequency and at 60GHz components such as: transmit receive filters, passives and antennas are candidates for inclusion on the die. Integrating RF, mixed signal and digital components is another important step towards reducing system cost and form factor. In order to achieve low cost and high digital integration CMOS is the process of choice. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages all of which make millimeter wave RF design particularly challenging. In this paper we outline the issues in the implementation of a Gigabit per second 60GHz Transceiver-on-Chip using CMOS.

Implementation of a Gigabit Per Second Millimetre Wave Transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds, are smaller in size, and have lower power consumption and cost. This motivates research to develop transceiver-on-chip and transceiver-in-a-package technologies. Recent advances in millimetre wave electronics have meant that significant portions of the system can now be integrated onto a single substrate or package. In order to achieve low costs and high digital integration CMOS is the process of choice as CMOS is the standard and a cost effective process for building digital circuits. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages. This makes millimetre wave wireless transceiver on a chip design particularly challenging. In this paper we outline the development of a gigabit transceiver-on-chip using CMOS and outline the performance of the fabricated components.

A 60-GHz direct-conversion transmitter in 130-nm CMOS

This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.

An LO power distribution network design for integrated 60-GHz transceiver on chip

This paper presents a local oscillation (LO) distribution network for the purpose of power splitting and distribution from a voltage-controlled oscillator (VCO) to a transmitter (Tx), receiver (Rx) and phase-locked loop (PLL) frequency synthesizer for an on-chip 60-GHz transceiver. The proposed LO distribution network architecture includes one input port and three output ports. The network circuit consists of four differential amplifiers to generate sufficient LO power and several transmission lines for power splitting and impedance matching. Since the proposed 60-GHz transceiver is based on a sub-harmonic direct-conversion architecture, the LO distribution network operates at 30-GHz frequency band. In simulation, the peak power gain of 8 dB occurs at 29.5 GHz, and the 3 dB bandwidth range is from 27.7 GHz to 32.1 GHz for each output port. The simulated output referred 1 dB compression point (OP1dB) is +7 dBm and the saturated output power is + 10 dBm. The DC power consumption is 78 mW under a 1.5 V supply. The LO distribution network circuit is integrated with the 60-GHz transceiver and fabricated in 65nm CMOS1.