Zongru Liu

A 60-GHz transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds are smaller in size with lower power consumption and cost than existing technology consequently high speed transceivers operating at 60 GHz and delivering multi-gigabit per second are receiving significant research interest. This paper describes a 60-GHz transmitter developed and tested on a 130-nm CMOS process.

Issues in the Implementation of a 60GHz Transceiver on CMOS

The spectrum around 60 GHz is available for unlicensed operation in many regulatory domains including the USA, Japan, Canada and Australia. One of the applications of this spectrum is for short range communication systems. These systems are designed to deliver gigabit speeds, consuming small amount of power in small form factor. The small factor is achieved because passive components scale with carrier frequency and at 60GHz components such as: transmit receive filters, passives and antennas are candidates for inclusion on the die. Integrating RF, mixed signal and digital components is another important step towards reducing system cost and form factor. In order to achieve low cost and high digital integration CMOS is the process of choice. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages all of which make millimeter wave RF design particularly challenging. In this paper we outline the issues in the implementation of a Gigabit per second 60GHz Transceiver-on-Chip using CMOS.

Implementation of a Gigabit Per Second Millimetre Wave Transceiver on CMOS

Modern systems require transceivers that deliver gigabit speeds, are smaller in size, and have lower power consumption and cost. This motivates research to develop transceiver-on-chip and transceiver-in-a-package technologies. Recent advances in millimetre wave electronics have meant that significant portions of the system can now be integrated onto a single substrate or package. In order to achieve low costs and high digital integration CMOS is the process of choice as CMOS is the standard and a cost effective process for building digital circuits. Unfortunately compared to other much more expensive processes such as SiGe and GaAs, CMOS has greater process variability, lower carrier mobility constants, and smaller device breakdown voltages. This makes millimetre wave wireless transceiver on a chip design particularly challenging. In this paper we outline the development of a gigabit transceiver-on-chip using CMOS and outline the performance of the fabricated components.

A 60 GHz VCO with 6GHz tuning range in 130 nm bulk CMOS

The IEEE 802.15.3c standards committee is working towards developing a standard that operates in the 57-66 GHz range and delivers data rates in the many gigabits per second range for devices communicating over a few meters. A 60 GHz cross-coupled differential voltage controlled oscillator is designed in 130 nm CMOS technology. The tuning range is from 64 GHz to 70 GHz, with a measured phase noise of -90.7 dBc/Hz at 1 MHz offset. The oscillator employs fundamental 30 GHz VCO with push-push output followed by buffers.

A 60-GHz direct-conversion transmitter in 130-nm CMOS

This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.

A 70GHz VCO with 8GHz Tuning Range in 0.13um CMOS Technology

A 70 GHz VCO with 8 GHz tuning range is implemented on 0.13um CMOS. It has an output power of - 4 dBm and a phase noise of -107 dBc/Hz at 10 MHz carrier offset. From 0 to 70 degree Celsius the output power varies from -4 dBm to -8 dBm and exhibits a maximum frequency deviation of 200 MHz over this range. The VCO has the highest figure of merit (-169.8dBc/Hz) of any VCO fabricated on bulk CMOS operating above 60 GHz.

Phase noise reduction techniques for multigigabit per second OFDM systems operating at 60 GHz

The IEEE 802.15.3C standards committee is working towards developing a standard that operates in the 57-64 GHz range and delivers data rates in the many gigabits per second range for devices communicating over a few meters. Multi carrier modulation schemes like orthogonal frequency division multiplexing (OFDM) and single carrier schemes like single carrier block transmission (SCBT) are being considered. It has been reported that OFDM systems are susceptible to poor performance in high phase noise environments. Unfortunately because implementations of millimetre-wave systems on current CMOS processes require active devices to operate at a significant fraction of the device transit frequency, high levels of phase noise are produced. In this paper we describe a modification to the long training preamble and new algorithms to mitigate the effects of phase noise for 802.15.3c OFDM systems built on CMOS operating at millimetre wavelengths.