Byung Chul Jang

Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition

Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices.

Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices.

Multilevel resistive switching nonvolatile memory based on MoS2 nanosheet-embedded graphene oxide

An increasing demand for nonvolatile memory has driven extensive research on resistive switching memory because it uses simple structures with high density, fast switching speed, and low power consumption. To improve the storage density, the application of multilevel cells is among the most promising solutions, including three-dimensional cross-point array architectures. Two-dimensional nanomaterials have several advantages as resistive switching media, including flexibility, low cost, and simple fabrication processes. However, few reports exist on multilevel nonvolatile memory and its switching mechanism. We herein present a multilevel resistive switching memory based on graphene oxide (GO) and MoS2 fabricated by a simple spin-coating process. Metallic 1T-MoS2 nanosheets, chemically exfoliated by Li intercalation, were successfully embedded between two GO layers as charge-trapping sites. The resulting stacks of GO/MoS2/GO exhibited excellent nonvolatile memory performance with at least four resistance states, >102 endurance cycles, and >104 s retention time. Furthermore, the charge transport mechanism was systematically investigated through the analysis of low-frequency 1/f noise in various resistance states, which could be modulated by the input voltage bias in the negative differential resistance region. Accordingly, we propose a strategy to achieve multilevel nonvolatile memory in which the stacked layers of two-dimensional nanosheets are utilized as resistive and charge-storage materials.

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for batterypowered flexible electronic systems.

Functional Circuitry on Commercial Fabric via Textile-Compatible Nanoscale Film Coating Process for Fibertronics

Fabric-based electronic textiles (e-textiles) are the fundamental components of wearable electronic systems, which can provide convenient hand-free access to computer and electronics applications. However, e-textile technologies presently face significant technical challenges. These challenges include difficulties of fabrication due to the delicate nature of the materials, and limited operating time, a consequence of the conventional normally on computing architecture, with volatile power-hungry electronic components, and modest battery storage. Here, we report a novel poly(ethylene glycol dimethacrylate) (pEGDMA)-textile memristive nonvolatile logic-in-memory circuit, enabling normally off computing, that can overcome those challenges. To form the metal electrode and resistive switching layer, strands of cotton yarn were coated with aluminum (Al) using a solution dip coating method, and the pEGDMA was conformally applied using an initiated chemical vapor deposition process. The intersection of two Al/pEGDMA coated yarns becomes a unit memristor in the lattice structure. The pEGDMA-Textile Memristor (ETM), a form of crossbar array, was interwoven using a grid of Al/pEGDMA coated yarns and untreated yarns. The former were employed in the active memristor and the latter suppressed cell-to-cell disturbance. We experimentally demonstrated for the first time that the basic Boolean functions, including a half adder as well as NOT, NOR, OR, AND, and NAND logic gates, are successfully implemented with the ETM crossbar array on a fabric substrate. This research may represent a breakthrough development for practical wearable and smart fibertronics.

Experimental study on quantum mechanical effect for insensitivity of threshold voltage against temperature variation in strained SOI MOSFETs

The temperature dependence of threshold voltage (VT) in a thin-body MOSFET, which was built on a strained silicon-on-insulator (sSOI) wafer, is examined in a temperature range of 173 K to 373 K. The insensitive temperature dependency of threshold voltage (VT) is attributed to the strain effect arisen from the sSOI, which makes the energy quantization stronger due to the lowered conductivity mass. Additionally, enhanced mobility of 770 cm2/V·sec at room temperature is achieved due to the strain effect.

Floating gate memory based on MoS 2 channel and iCVD polymer tunneling dielectric

We investigated the floating gate memory based on MoS2 channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable distribution of charge trapping layer, different thickness of gold nanoparticles via thermal evaporation method was used. Al2O3 blocking dielectric is deposited via atomic layer deposition (ALD) process to increase gate coupling ratio for low power operation. The fabricated floating gate memory device exhibits tunable memory window with a high on/off ratio after applied programming and erasing pulse, allowing for multi-bit data storage with a long retention Ion/off ratio. All these results will be a foundation stone for the development of floating gate memory based on MoS2.