Junhwan Choi

Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition

Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices.

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic (MAGIC) architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for batterypowered flexible electronic systems.

Flexible, Low-Power Thin-Film Transistors Made of Vapor-Phase Synthesized High-k, Ultrathin Polymer Gate Dielectrics

A series of high-k, ultrathin copolymer gate dielectrics were synthesized from 2-cyanoethyl acrylate (CEA) and di(ethylene glycol) divinyl ether (DEGDVE) monomers by a free radical polymerization via a one-step, vapor-phase, initiated chemical vapor deposition (iCVD) method. The chemical composition of the copolymers was systematically optimized by tuning the input ratio of the vaporized CEA and DEGDVE monomers to achieve a high dielectric constant (k) as well as excellent dielectric strength. Interestingly, DEGDVE was nonhomopolymerizable but it was able to form a copolymer with other kinds of monomers. Utilizing this interesting property of the DEGDVE cross-linker, the dielectric constant of the copolymer film could be maximized with minimum incorporation of the cross-linker moiety. To our knowledge, this is the first report on the synthesis of a cyanide-containing polymer in the vapor phase, where a high-purity polymer film with a maximized dielectric constant was achieved. The dielectric film with the optimized composition showed a dielectric constant greater than 6 and extremely low leakage current densities (<3 × 10-8 A/cm2 in the range of ±2 MV/cm), with a thickness of only 20 nm, which is an outstanding thickness for down-scalable cyanide polymer dielectrics. With this high-k dielectric layer, organic thin-film transistors (OTFTs) and oxide TFTs were fabricated, which showed hysteresis-free transfer characteristics with an operating voltage of less than 3 V. Furthermore, the flexible OTFTs retained their low gate leakage current and ideal TFT characteristics even under 2% applied tensile strain, which makes them some of the most flexible OTFTs reported to date. We believe that these ultrathin, high-k organic dielectric films with excellent mechanical flexibility will play a crucial role in future soft electronics.

Vapor-phase synthesis of sub-15 nm hybrid gate dielectrics for organic thin film transistors

Organic thin film transistors (OTFTs) have been extensively investigated for next-generation electronic devices. However, many of them still suffer from poor device performances, which limits their real-world applications. The use of high-k oxides such as Al2O3via atomic layer deposition (ALD) can mitigate this issue by increasing the capacitance of the dielectric layer (Ci). However, the abundant –OH functionality at the surface of oxides, and the ionic polarization between the carrier and high-k ionic lattice cause severe hysteresis, drop of mobility, and shift of threshold voltage in OTFTs. Low mechanical flexibility of the layers is also problematic, which hinders the broad use of ALD layers for flexible electronics. To address this issue, we synthesized an ultrathin (<15 nm) and mechanically flexible high-k oxide/non-polar polymer hybrid layer by integrating the ALD and initiated chemical vapor deposition (iCVD) processes into one chamber. The non-polar polymer via iCVD efficiently passivated the polar surface of the Al2O3 layer even with the thickness lower than 4 nm, which was hard to achieve with the conventional solution-based processes. Through the systematic variation of the polymer thickness, it turned out that the hybrid dielectric layer exhibited substantial improvement of overall device performances and long term operation stability against the continuous voltage stress (CVS) for 3000 s. The resulting 15 nm-thick hybrid layer even withstood a tensile strain up to 3.3%, which is far superior to the mechanical flexibility of the Al2O3 layer. Both the hybrid dielectric layer and the new vacuum process are expected to be highly beneficial for realizing high-performance transistors with mechanical flexibility.

Vapor-phase deposition of the fluorinated copolymer gate insulator for the p-type organic thin-film transistor

ABSTRACT A copolymer-based gate insulator was synthesized from 1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane (V3D3) and 3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluorodecyl methacrylate (PFDMA) via initiated chemical vapor deposition. The synthesis of the random copolymer of poly(V3D3-co-PFDMA) was confirmed by Fourier transform infrared, X-ray photoelectron spectroscopy, and water contact angle analysis. No phase segregation and pinhole formation were observed in the atomic force microscopy images of the copolymer film. The ultra-thin copolymer film showed an extremely low leakage current density (J < 10−9 A/cm2 in the range of ±2 MV/cm) even with a 70 nm thickness. Pentacene organic thin-film transistors (OTFTs) were fabricated with the copolymer gate insulator and showed excellent operational stability. An up to 95% initial drain current was maintained, and a negligible shift in threshold voltage (VT) was observed even after applying a constant gate bias stress of −12 V and a corresponding electric field of 1.7 MV/cm to the OTFT for 3 ks.

Floating gate memory based on MoS 2 channel and iCVD polymer tunneling dielectric

We investigated the floating gate memory based on MoS2 channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable distribution of charge trapping layer, different thickness of gold nanoparticles via thermal evaporation method was used. Al2O3 blocking dielectric is deposited via atomic layer deposition (ALD) process to increase gate coupling ratio for low power operation. The fabricated floating gate memory device exhibits tunable memory window with a high on/off ratio after applied programming and erasing pulse, allowing for multi-bit data storage with a long retention Ion/off ratio. All these results will be a foundation stone for the development of floating gate memory based on MoS2.