Gwang Hyuk Shin

Multilevel resistive switching nonvolatile memory based on MoS2 nanosheet-embedded graphene oxide

An increasing demand for nonvolatile memory has driven extensive research on resistive switching memory because it uses simple structures with high density, fast switching speed, and low power consumption. To improve the storage density, the application of multilevel cells is among the most promising solutions, including three-dimensional cross-point array architectures. Two-dimensional nanomaterials have several advantages as resistive switching media, including flexibility, low cost, and simple fabrication processes. However, few reports exist on multilevel nonvolatile memory and its switching mechanism. We herein present a multilevel resistive switching memory based on graphene oxide (GO) and MoS2 fabricated by a simple spin-coating process. Metallic 1T-MoS2 nanosheets, chemically exfoliated by Li intercalation, were successfully embedded between two GO layers as charge-trapping sites. The resulting stacks of GO/MoS2/GO exhibited excellent nonvolatile memory performance with at least four resistance states, >102 endurance cycles, and >104 s retention time. Furthermore, the charge transport mechanism was systematically investigated through the analysis of low-frequency 1/f noise in various resistance states, which could be modulated by the input voltage bias in the negative differential resistance region. Accordingly, we propose a strategy to achieve multilevel nonvolatile memory in which the stacked layers of two-dimensional nanosheets are utilized as resistive and charge-storage materials.

Pyridinic-N-Doped Graphene Paper from Perforated Graphene Oxide for Efficient Oxygen Reduction

We report a simple approach to fabricate a pyridinic-N-doped graphene film (N-pGF) without high-temperature heat treatment from perforated graphene oxide (pGO). pGO is produced by a short etching treatment with hydrogen peroxide. GO perforation predominated in a short etching time (∼1 h), inducing larger holes and defects compared to pristine GO. The pGO is advantageous to the formation of a pyridinic N-doped graphene because of strong NH3 adsorption on vacancies with oxygen functional groups during the nitrogen-doping process, and the pyridinic-N-doped graphene exhibits good electrocatalytic activity for oxygen reduction reaction (ORR). Using rotating-disk electrode measurements, we confirm that N-pGF undergoes a four-electron-transfer process during the ORR in alkaline and acidic media by possessing sufficient diffusion pathways and readily available ORR active sites for efficient mass transport. A comparison between Pt/N-pGF and commercial Pt/C shows that Pt/N-pGF has superior performance, based on its more positive onset potential and higher limiting diffusion current at −0.5 V.

Vertical-Tunnel Field-Effect Transistor based on Silicon-MoS2 3D-2D Heterostructure

We present a tunneling field-effect transistor based on a vertical heterostructure of highly p-doped silicon and n-type MoS2. The resulting p-n heterojunction shows a staggered band alignment in which the quantum mechanical band-to-band tunneling probability is enhanced. The device functions in both tunneling transistor and conventional transistor modes, depending on whether the p-n junction is forward or reverse biased, and exhibits a minimum subthreshold swing of 15 mV/dec, an average of 77 mV/dec for four decades of the drain current, a high on/off current ratio of approximately 107 at a drain voltage of 1 V, and fully suppressed ambipolar behavior. Furthermore, low-temperature electrical measurements demonstrated that both trap-assisted and band-to-band tunneling contribute to the drain current. The presence of traps was attributed to defects within the interfacial oxide between silicon and MoS2.

Floating gate memory based on MoS 2 channel and iCVD polymer tunneling dielectric

We investigated the floating gate memory based on MoS2 channel with metal nanoparticle charge trapping layer and polymer tunneling dielectric. Here, highly conformal and stable polymer insulator layer deposited via initiated chemical vapor deposition (iCVD) facilitates the fabricated floating gate memory to endure a substantial electrical stress significantly. To form a selective density and controllable distribution of charge trapping layer, different thickness of gold nanoparticles via thermal evaporation method was used. Al2O3 blocking dielectric is deposited via atomic layer deposition (ALD) process to increase gate coupling ratio for low power operation. The fabricated floating gate memory device exhibits tunable memory window with a high on/off ratio after applied programming and erasing pulse, allowing for multi-bit data storage with a long retention Ion/off ratio. All these results will be a foundation stone for the development of floating gate memory based on MoS2.