Jeong-Hyeon Cho

A compact, low-cost, and wide-band passive equalizer design using multi-layer PCB parasitics

In this work, we developed a sophisticated low-cost and wide-band passive equalization method for high-speed differential interconnects. The proposed method was based on a high-pass filter design using parasitics that exist in multi-layer printed circuit board (PCB) interconnects. By employing the parasitics as the filter design components, the proposed passive equalization method offered low-cost and wide-band performance in a compact area. A noticeable improvement in the timing jitter and eye-opening using the proposed passive equalizer was demonstrated for a data rate of 20 Gbps.