C.C. Chiu

Interfacial Fracture Analysis of CMOS Cu/Low-

The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.

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Purpose – The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.Design/methodology/approach – The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.Findings – To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite el...

BEOL Interconnect in Advanced Packaging Structures

Thermal impact on back-end interconnects resulted from self-heating (SH) effect in FinFET devices is investigated here. The self-heating effect in FinFET devices will generate more heat in fin structures than planar devices and influence the reliability of interconnects. In this study, testing structures including metal sensors of different metal layers are designed, fabricated and measured, as well as a computer-aided finite element model is also built and utilized in this report. With FinFET devices, the evaluation includes temperature saturation with the number of powered devices, temperature rising in different metal layer, and self-heating effect accompanying with joule heating (so-called coupling effect). This investigation shows the contribution of SH effect would change with varying joule heating. It is important to considering the temperature rising from SH effect when assess the risk of back-end interconnects reliability.

A novel crack and delamination protection mechanism for a WLCSP using soft joint technology

As the technology of the semiconductor process continues to move forward, the next generation IC chip with copper/low-k stacked structures is being developed for reducing the RC delay in order to obtain high-speed signal communication. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper interconnections and the low-k material as a result of poor adhesion and lower fracture toughness of the low-k material when temperature loads are applied during the wafer level and the packaging level stages. This fracturing problem is one of the most urgent issues for the thermo-mechanical reliability of a copper/low-k damascene module, and it needs to be resolved urgently. With the simulation of an interfacial fracture based on J-integral value estimation, the interfacial crack growth can be modeled using a finite element analysis (FEA) and compared it to Jc, which is interfacial fracture toughness that must be determined experimentally. Therefore, the stability of the J-integral value obtained from the FEA is crucial so as to avoid a misunderstanding of the cracking energy. In order to discuss the mesh density affecting the convergence of the J-value, various paths with an integral contour surrounding the crack tip are considered in this research. The interfacial crack is constructed using the element birth and death technique to suppose that an actual crack developed between copper/low-k interfaces. The analytic results show that the J-value will converge toward unity when a rectangular contour with a proper ratio of length/width, and multi-layers of element close to the delaminating surfaces are applied to reduce the loss of numerical analysis in precise. It should be noted that the crack tip must be at the center of the integral contour. The long side of the rectangular contour needs to be parallel to the direction of the fracture propagation. On the other hand, the curve of the J-value versus the increase of the crack length calculated from the model with the actual crack embedded shows good agreement with the simulated results with the virtual crack by means of the element birth and death technique

Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects

Abstract As is well known, the design parameters of the packaging material and structure greatly influence the reliability of the packaging. When it comes to flip chip packages, the package reliability design becomes more complicated. In addition, the interactions between these different design parameters remain unclear, especially for lead‐free solder applications. Based on the above, FEM factorial analysis was employed in this study to investigate the interrelationship of the design parameters. A factorial analysis with two levels and five factors was chosen. The factors included pre‐solder thickness, thickness of the BT core in the laminate substrate, bumping height, substrate side pad opening, and the climbing height of the underfill. The factorial design method was repeated twice with two kinds of solder bump materials (63Sn/37Pb and 96.5Sn/3.5Ag). The findings show that the structures with the larger BT core thickness, thicker pre‐solder layer and higher bump height have the better solder bump reliability. In terms of the factorial analysis, the BT core thickness was the factor having the most influence on reliability. The interactions between the factors were observed in this study.

Stability of J-integral calculation in the crack growth of copper/low-K stacked structures

In this paper, a thermal enhanced design for a high power density system in package (SiP) is proposed to resolve the challenge faced by the packaging research community in eliminating the hot spot and reducing the junction temperature in a high operation temperature. The SiP structure includes seven sub-chips which are attached to the chip carrier. The dissipated heat is conducted to the metal slug by thermal vias, while some heat is conducted to the pads by metal traces. Finally, the whole module is connected to the test board by solder paste material. In the thermal enhanced design, a highly conductive material such as solder paste is applied to make an attachment between the chip carrier and the highest power density chip (the power amplifier chip). Besides, some thermal vias are constructed to conduct the dissipated heat from the chip carrier to the metal slug. The new structure greatly improves the thermal performance of the SiP structure. Moreover, the hot spot on the chip carrier is also eliminated in this thermal enhanced SiP structure.Copyright

Failure life prediction and factorial design of lead‐free flip chip package

Insulated gate bipolar transistors (IGBT) have been utilized in high power and fast switching applications for power management. Research on transient thermal performance assessment has become imperative because of the excessive heat generated from the IGBT chip. In this study, the transient thermal performance of the power chip under the power cycling test was investigated, and the temperature history on the chip was recorded by an infrared thermometer during the test. The test conditions of the experiment were based on: the International Electrotechnical Commission (IEC) standard. The current density distribution of the IGBT chip was investigated by electro-thermal finite element (FE) analysis. In order to validate the methodology for FE analysis, the predicted temperature distribution was compared with the experimental data under the same electrical load. Furthermore, the temperature-dependent material property was employed in electro-thermal FE analysis. The results show that the current crowding effect occurred near the periphery of the bonding wires. Moreover, the solder under the chip provided a significant route of heat dissipation in the power chip, when high power was applied.

Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure

Sub-micron Cu damascene interconnect, electromigration is mainly due to the diffusion at the interfaces of Cu with liner or dielectric capping layer. Many reports have pointed out the Cu/capping dielectric as the dominant interface. Experiments were performed to study the effect of the Cu line width and stress current direction on electromigration. For Cu line with multiple via connections, the resistance to electromigration is influenced by the metal width regardless of the electron flow direction. On the other hand, in case of a single via connection structure, the results revealed significant differences in electromigration behavior for up-stream and down-stream stress. For the up-stream stress, EM behavior is dominated by Cu drift velocity. Wider metal lines have the lower Cu drift velocity, and so possess the better EM resistance. In the case of down-stream stress, two distinct failure modes, via bottom and metal line depletion, were found, thus worsening the lifetime distribution due to higher current in the via bottom for the wider metal. Two effective methods, enlarging via size and enhancing Cu/capping process, were demonstrated to improve the EM distribution in this study

Thermal design and transient analysis of insulated gate bipolar transistors of power module

Stress-induced voiding (SIV) at a narrow metal line connected to a wide metal plate is investigated for Cu/low-k interconnects. Different from the traditional stress migration failure modes of voiding underneath the via or inside the via, new failure modes due to void formation in the narrow metal line have been observed in highly scaled Cu/low-k interconnects. Using the SIV data extracted from different geometries of test patterns, the narrow metal line related SIV failure mechanism resulted from a wide metal plate as vacancies reservoir and stress gradient in the connection of the narrow metal line to the wide metal is discovered and characterized. Process improvement which enhanced the adhesion between metallization and ILD interface has been shown to effectively reduce the vacancy migration and suppress the new failure modes.

Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration

The short length on the electromigration lifetime is a useful effect to increase current limits in advanced circuits. A way to increase current limit is to consider the Blech effect. The electromigration threshold due to Blech effect in copper interconnect for 65 nm and 45 nm technology is reported in this study. The critical product (jL)c was determined by varying the metal length and stress current density. The higher (jL)c value is obtained for lower stress current, shorter metal lead and 65 nm technology with higher hardness ILD. Finally, this critical product (jL)c as the accelerated EM length factor was used to predict the lifetime. It is shown that the lifetimes of short leads with less than 5 mum have at least 9.52 and 1.45 times higher than that of 250 mum metal lead for 65 nm and 45 nm technology, respectively.