Kuo-Ning Chiang

An overview of solder bump shape prediction algorithms with validations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range.

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

Current crowding-induced electromigration in SnAg3.0Cu0.5 microbumps

To determine the relevance of current crowding to electromigration in the SnAg3.0Cu0.5 solder bump, a three-dimensional dual bumps simulation model was designed to demonstrate how current crowding can enhance the local atomic flux along the electron flow path. The finding of void formation occurred at the entrance points to the cathode sides and the enhancement of the growth and clustering of the intermetallic compound at the outgoing points of the anode sides along the electron flow path were verified experimentally. The tilting effect is obvious at the anode/chip side. The experimental mean-time-to-failure was observed, and Black’s equation with Joule heating effect were investigated as well.

On enhancing eutectic solder joint reliability using a second-reflow-process approach

A three-dimensional (3-D) solder liquid formation model is developed for predicting the geometry, the restoring force and the reliability of solder joints in an area array of interconnects [e.g., ball grid array (BGA), flip chip] with various pad configurations. In general, the restoring force and the reliability of the solder joints depend on the thermal-mechanical behavior of the solder, the geometry of the solder ball, and the geometry layout/material properties of the package. A good solder pad configuration could lead to a larger restoring force along the gravitational direction (a higher standoff height and a blunter contact angle) with better reliability characteristics achieved. In this research, a second-reflow-process approach is applied for the reliability enhancement of typical EGA assemblies, including PBGA and SuperBGA assemblies. The results show that for a typical PBGA assembly, the ratio of the enhancement by application of the second-reflow-process approach is 2.03 based on the Coffin-Manson criterion and 1.4 based on the energy density based method, and more significantly, for a typical SuperBGA assembly, it is 7.17 and 2.422, respectively.

Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array

The increasing need to create high density and fine pitch electronic interconnections presents a number of challenges. The fatigue-induced solder joint failure of surface mounted electronic devices has become one of the most critical reliability issues in electronic packaging industry. Prediction of the shape of solder joint has drawn special attention in the development of electronic packaging for its practical engineering application. Many solder joint models have been developed based on energy minimization principle (Patra et al, 1995) or analytical method (Heinrich et al, 1993, Liedtke 1993). These methods are extensively utilized to the shape design of solder joint. However, it is important to find a suitable method in real application. In this study, an efficient numerical method used to predict the shapes of solder joint is investigated and the results are compared with Surface Evolver program. The changes of geometric shape with respect to different parameters of solder joint are also discussed in this paper. The influences of the geometric parameters such as volumes of solder joint, package weight, contact angles, pads sizes, solder surface tension, and gravity forces to the shape of solder joint are investigated. Results presented in this study can be used to determined the optimal balanced stand-off height of Single Ball Module (SBM) or Multiple Ball Module (MBM) solder joint models.

Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Packages

1 Associate Professor, Corresponding author 2 Graduate Assistant Abstract Development of flip-Chip-on-glass (FCOG) assembly technology using anisotropic conductive adhesive/film (ACA/ACF) is currently underway to achieve fine pitch interconnections between driver IC and flat panel display. Conductive adhesives are characterized by fine-pitch capability and more environment compatibility. Anisotropic conductive adhesive/film (ACA/ACF) is composed of an adhesive resin and conductive particles, such as metallic or metal-coated polymer particles. In contrast to a solder type flip chip interconnection, the electric current passing through conductive particles becomes the dominant conduction paths. The interconnection between the particles and the conductive surfaces is constructed by the elastic/plastic deformation of conductive particles with contact pressure, which is maintained by tensile stress in the adhesive. Although loss of electric contact can occur when the adhesive expands or swells in the Z-axis direction, delamination and cracking can occur in the adhesive layer while the tensile stress is excessive. In addition to performing processing simulations as well as reliability modeling, this research investigates the contact force that is developed and relaxed within the interconnection during the process sequence by using nonlinear finite element simulations. Environmental effects such as high temperature and thermal loading are also discussed. Moreover, a parametric study is performed for process design. To improve performance and reliability, variables such as ACF materials, proper processing conditions are discussed as well. Furthermore, this study presents a novel method called equivalent spring method, capable of significantly reducing the analysis CPU time and make process modeling and contact analysis of the 3D ACA/ACF process possible.

Time and temperature-dependent mechanical behavior of underfill materials in electronic packaging application

Abstract The thermo-mechanical testing of HYSOL FP4549 polymer-filled underfill materials was conducted under different strain rate and temperature environment. A new specimen preparation procedure and further test methodology are developed to characterize the time–temperature mechanical behaviors of underfill materials. The stress–strain behavior of materials is simulated with constitutive framework, and the dependence of Young’s modulus on temperature and strain rate was evaluated. In addition, the specimens were tested with microforce testing system to evaluate the creep curve of underfill materials as a function of temperature and stress level. In view of the uncertainty of the Young’s modulus determination, the specimens were tested with unloading–reloading technique to verify the test results and investigate its cyclic mechanical behaviors. On the other hand, the adhesion strength of underfill materials are tested between different adhesion surface by different deformation rate after some isothermal and hygro-thermal environments attack, which is to simulate the environment that the electronic components may be encountered. The results reveal that the rise of the temperature and moisture cause the apparent reduction of the surface adhesion strength, due to the microstructure transition of materials and the diffusion and concentration of moisture. For all conditions of the experiment after environmental preconditioning, the specimen fracture surfaces occur between solder mask and FR4 substrates, which means the measured strength is the adhesion strength between solder mask and FR4. Comparing different adhesion surface, the adhesion strength of underfill/FR4 is higher than solder mask/FR4. The interface of solder mask/FR4 is more sensitive to the temperature and moisture. In all of the cases, increasing the moisture level has a varying but significant effect on both fracture strength and absorption energy Ψ. The failure mode transfer and the strength degradation are attributed to the moisture uptake between the FR4/solder mask and solder mask/underfill interface.

Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module

Light emitting diode (LED) with a long lifetime, low power consumption, and low pollution has been successfully applied in many products. However, due to its low electro-optical conversion efficiency, high percentage of input power transformed to redundant heat, thus increasing the LED temperature. This phenomenon decreases the luminous flux, changing light color, and useful life span of LED. Therefore, thermal management becomes an important issue in high power LED. In this paper, the variation of luminous flux and light color for different LED lighting modules under long time operation has been measured and discussed. In addition, a detailed finite element model of LED lighting module, MR-16, with a corresponding input power and suitable boundary conditions is established by using the ANSYS finite element analysis program. Furthermore, to validate the simulation results, the current-voltage-temperature method for characterization of a diode is utilized to measure the junction temperature of LED chip indirectly and compare with simulation results. After the simulation is validated, various thermal performance assessments under the different design parameters of the LED package and lighting module are also investigated in this paper. The methodology and analysis results of this paper can provide a guideline for the LED lighting module such as MR-16 design in the future.

Analysis of Thermal Performance of High Power Light Emitting Diodes Package

This paper reports on the thermal characteristics of the high power LED package. The increment of input power generates more heat in the chip, decreasing the luminance and life span of LEDs. To enhance the efficiency of high power LEDs, challenges related to thermal management need to be addressed. In this research, a detailed finite element model of the high power LED package with proper input power and boundary condition is established using the ANSYS@ finite element analysis program. The applied input power is 1W on GaN, and the convection coefficient is adopted from Williams experimental results. Radiation is also included in the FEM model. Additionally, forward voltage methods used to indirectly measure the junction temperature are also performed to validate the finite element model with predicted input power. The simulation results closely match the experimental data, with only 5% error. Various thermal performances under different design parameters of the high power LED package are developed following verification of the simulation analysis. Five design factors including (a) the substrate of the chip, (b) the thickness of the die attach material (c) the electro-optical conversion efficiency (d) the thickness of the copper slug and (e) the area of the copper slug are chosen to determine themost dominant factor in this study. The factorial design provides a guide line for the compromise between thermal enhanced design and manufacturing process in the future.

Thermal–mechanical behavior of the bonding wire for a power module subjected to the power cycling test

Abstract Two analytical methods were proposed in this research, coupled electro-thermal finite element (FE) analysis and thermal–mechanical FE analysis, to analyze the mechanical behavior of bonding wire of power module under cyclic power loads, and the International Electrotechnical Commission standard is adopted in conducting a power cycling test. The exterior temperature distribution was measured by an infrared thermometer. Moreover, the junction temperature is calculated from the given thermal impedance of the semiconductor chip, chip power loss, and case temperature. Subsequently, the simulated temperature distribution via electro-thermal FE analysis is compared with experimental results to validate the methodology used in the aforementioned analysis. The analysis shows compressive stress at the wire/chip interface due to CTE mismatch between the aluminum and the chip. Moreover, the major driving force contributing to the shear stress at the interface is the self-expansion of the wire bump.