Chung-Jung Wu

Charge imaging and manipulation using carbon nanotube probes

Due to their high aspect ratio, well-defined cylindrical structure, and good electrical conductivity, carbon nanotubes (CNTs) are ideal probes for “true” local imaging of electric domain structures at the nanoscale. By performing force–distance measurements and tip-shape profiling with a uniformly charged oxide square, we clearly demonstrate the local nature of the CNT tip for electrostatic force microscopy. We show that CNTs can be used to probe long-range electrostatic forces with a lateral resolution better than 5 nm.

Prediction of the bulk elastic constant of metals using atomic-level single-lattice analytical method

An atomic-level single-lattice method with a closed-form equation is presented to predict the elastic characteristics of bulk metals. In this letter, the interatomic forces of single body-centered-cubic (bcc) and face-centered-cubic (fcc) lattices are described as atomic springs, the single bcc and fcc lattices are therefore constructed as simple spring network models. The analytical result indicates that the calculated single-lattice elastic characteristics and the experimental bulk values are within a reasonable range. This analytical equation also provides a feasible way of taking a second look at the Morse potential coefficients of metallic atoms.

Trace line failure analysis and characterization of the panel base package (PBP™) technology with fan-out capability

The wafer level package (WLP) is a cost-effective solution for the electronic package, and has been increasingly applied during recent years. In this study, a new packaging technology developed based on the concepts of the WLP, the panel base package (PBP) technology, is proposed in order to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface, and the pitch of the chip side is fanned-out. The design concept and the manufacturing process of the PBP would first be described in this study. The three-dimensional finite element (FE) model is established based on the real testing sample, and the thermo-mechanical behavior of the PBP is simulated. It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer (SBL). However, the accumulated stress/strain from the coefficient of thermal expansion (CTE) mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid the stress concentration effect.

Failure life prediction and factorial design of lead‐free flip chip package

Abstract As is well known, the design parameters of the packaging material and structure greatly influence the reliability of the packaging. When it comes to flip chip packages, the package reliability design becomes more complicated. In addition, the interactions between these different design parameters remain unclear, especially for lead‐free solder applications. Based on the above, FEM factorial analysis was employed in this study to investigate the interrelationship of the design parameters. A factorial analysis with two levels and five factors was chosen. The factors included pre‐solder thickness, thickness of the BT core in the laminate substrate, bumping height, substrate side pad opening, and the climbing height of the underfill. The factorial design method was repeated twice with two kinds of solder bump materials (63Sn/37Pb and 96.5Sn/3.5Ag). The findings show that the structures with the larger BT core thickness, thicker pre‐solder layer and higher bump height have the better solder bump reliability. In terms of the factorial analysis, the BT core thickness was the factor having the most influence on reliability. The interactions between the factors were observed in this study.

Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure

In this paper, a thermal enhanced design for a high power density system in package (SiP) is proposed to resolve the challenge faced by the packaging research community in eliminating the hot spot and reducing the junction temperature in a high operation temperature. The SiP structure includes seven sub-chips which are attached to the chip carrier. The dissipated heat is conducted to the metal slug by thermal vias, while some heat is conducted to the pads by metal traces. Finally, the whole module is connected to the test board by solder paste material. In the thermal enhanced design, a highly conductive material such as solder paste is applied to make an attachment between the chip carrier and the highest power density chip (the power amplifier chip). Besides, some thermal vias are constructed to conduct the dissipated heat from the chip carrier to the metal slug. The new structure greatly improves the thermal performance of the SiP structure. Moreover, the hot spot on the chip carrier is also eliminated in this thermal enhanced SiP structure.Copyright

Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging

In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, -40degC ~ 125degC). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications.

Determination of maximum strength and optimization of LED chip structure

High-power light emitting diodes (LEDs) are found in a number of applications in high-volume consumer markets, such as illumination, signalling, screen backlights, automotives, and others, because of the numerous advantages of LEDs, including low power cost, long life span, and high efficiency. During the manufacturing process, the high-power LED chips are subjected to mechanical and thermal loadings. Wire bonding is one of the major processes in the LED packaging process that provide electrical interconnection between the bonding pad and the lead. However, due to bad parameter setup in a wire bonder, the LED will crack and the pad will peel after wire bonding. In this study, the strength of LED is determined for the design requirement in order to ensure good reliability of wire bonding. Pointload test (PLT) and focused ion beam (FIB) are used to determine the maximum allowable force the epilayer can withstand, which is approximately 75 g. By combining the finite element method and experimental data, a useful design tool to confirm LED die strength is provided. Finite element results of contact analysis show that the stress concentration area is located on the edge of the pin and maximum stress (227 MPa) occurs in the epilayer. Parametric study is employed to find ways to reduce stress in LED layer. The results indicate that increasing pad thickness is the major factor that can reduce stress and enhance LED die strength. PLT and FIB experiments are also performed to confirm simulation results.

Simulation and Validation of CNT Mechanical Properties - The Future Interconnection Material

The notable material properties of carbon nanotubes (CNTs) with ballistic electrical transport, ultrahigh Youngs modulus and thermal conductivity made them very attractive for microelectronic interconnections, thermal management and nanoscale device applications. This paper will focus on the analysis of mechanical properties of single-walled carbon nanotubes (SWCNTs). In our research, the atomistic-continuum mechanics (ACM) was applied to investigate the mechanical properties of SWCNTs. By establishing a linkage between structural mechanics and molecular mechanics, not only the Youngs moduli could be obtained but also the modal analysis could be achieved. In addition, according to atomistic-continuum mechanics and finite element method, an effective atomistic-continuum model is constructed to investigate the above two mechanical properties of SWCNTs with affordable computational time by personal computers. The validity of the results is demonstrated by comparing them with existing results. Furthermore, the ACM could provide an efficient method in the analysis of mechanical properties of the CNTs-refined electronic packaging structure.

Stress/stain assessment and reliability prediction of through silicon via and trace line structures of 3D packaging

This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the thermal-mechanical behavior of TSV. Subsequent thermal cycle simulations show that the maximum equivalent plastic strain occurs at the bottom trace near the substrate. The Engelmaier model is selected to predict the fatigue life of TSV, and it shows that the simulation results match experimental results. The effects of the substrate material and underfill are also discussed. TSV structures with BT substrates, which can replace silicon substrates, could effectively protect bottom traces and prevent fractures occurring from copper trace. In addition, when a TSV structure with an underfill is subjected to thermal cycle conditions, chips and vias experience more stress, but copper traces are protected by the underfill. No apparent alteration in reliability performance is detected.

Strength determination of light-emitting diodes and chip structure design

Light-emitting diodes (LEDs), representing a type of solid-state lighting, have been widely used as indicator lamps in the past few decades. It has attracted a great deal of attention in various illuminating applications in recent years due to its outstanding advantages, such as low power cost, long life time, and high efficiency. However, to make it possible to apply LED in daily life, a suitable package structure is necessary, which provides electrical interconnection and protection functions. Recently, the technology for a high power LED packaging that employs applied wire bonding process to achieve electrical interconnection has been widely adopted by LED packaging house. However, improper wire bonding parameters often result in LED die cracking or pad peeling. In this study, the strength of LED dies was investigated in order to improve the yielding of wire bonding. To determine its strength, point-load test associated with focusedion beam was utilized to measure the ultimate reactive force. Results of the experiment were further integrated with simulation technology based on the finite element method to evaluate its ultimate strength. In the PLT tests, direct contact pin-loading was applied to the epilayer surface of the LED dies and the ultimate force was measured. After the PLT tests, FIB was utilized to investigate fracture initiating location in the epilayer. The PLT results showed that the averaged ultimate force is about 75 g. According to the FIB results, the vertical load was validated as the driving force for pad peeling, epilayer crack, and LED die crack. Based on the experimental data, an FEM 3D contact model was utilized to analyze its detailed mechanical behaviours. Simulation results showed that stress concentration occurred near the edge of the pin and that the maximum stress took place in epilayer. In order to reduce the stress, three kinds of new LED structures that introduce the stress buffer layer between the Au pad and LED layers were evaluated, and the results showed good improvement of stress reduction in the epilayer. Nevertheless, the soft material applied for the stress buffer structure may cause another failure issue under thermal loading during the bonding process due to the mismatch of the coefficient of thermal expansion. Therefore, to achieve the optimal design and the best combination of design parameters, the simulation-based design methodology must be adopted to meet the design and production optimization goals, which would be impossible if done by conventional experiment-based trial-and-error design procedure.